用於類比仿真器中的波動數位濾波器自動建構及排程方法

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姓名

楊旭平(HSU-PING YANG) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於類比仿真器中的波動數位濾波器自動建構及排程方法
(Automatic Construction and Scheduling of the Wave Digital Filter Structures for Analog Emulators)

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摘要(中)

為了滿足下一世代半導體和電子產品的複雜設計所需，積體電路現今已經發展成為單晶片系統( System on Chip , SOC )，在單晶片系統架構中，需要處理包含數位訊號、類比訊號以及混合訊號，在設計過程中，設計者必須採取各種方式對晶片的邏輯功能進行驗證( Function Verification )，然而在傳統的設計流程中，類比電路以及數位電路，採用不同的設計以及驗證流程，使得系統整合與驗證變得非常困難，至今也尚未有一套標準的EDA 工具可以支援混合訊號系統的驗證。為了找出一套適用於類比電路系統級驗證的仿真方法，我們利用波動數位濾波器(Wave Digital Filter, WDF)將類比電路對映到數位電路上，最後將數位電路放入FPGA 中進行仿真，本篇論文將提出一套有效率以及可靠的自動化建構方法將類比電路轉換成波動數位濾波器架構，並解決轉換過程中會遇到的困難及瓶頸，最後在映射到數位電路前，為了找出最佳的關鍵路徑，我們將波動數位濾波器樹狀結構進行排程，以達到最佳效能。由實驗結果來看，本論文提出的方法確實有效的解決了WDF 轉換的問題，並成功地縮短了電路的延遲路徑。

摘要(英)

Nowadays, system-on-chip (SOC) designs become the mainstream of integrated circuits (ICs) to satisfy the customer demand for high-complexity electronic products. For SOC designs, it is common to deal with both digital signals and analog signals simultaneously. During the design process, designers have to ensure the function correctness through different functional verification flows. However, it is very difficult to simulate digital and analog circuits together in traditional design flows due to their different design approaches. Therefore, there is still no practical EDA tool to support the verification of mixed-signal systems.

In order to develop an emulation flow for analog circuits, we adopt Wave Digital Filter (WDF) theorems to transform analog behaviors into digital circuits, which can be put into FPGA for fast hardware emulation. In this thesis, an automatic transformation flow is proposed to solve the translation issues from circuit netlist to its corresponding WDF structure, with optimized tree height and number of adaptors. Furthermore, a dedicated scheduling algorithm is also proposed for the WDF tree structure to reduce the critical path and improve the emulation performance. As shown in the experimental results, the proposed algorithm is able to solve the automatic transformation issues for WDF structures and successfully reduce their critical path delay.

關鍵字(中)

★ 波動數位濾波器

關鍵字(英)

★ WDF

論文目次

摘要 .................................................................................................................................................... I
ABSTRACT .......................................................................................................................................... II
致謝 .................................................................................................................................................. III
目錄 ..................................................................................................................................................IV
圖目錄 ............................................................................................................................................ VII
表目錄 ............................................................................................................................................... X
第一章、緒論 .................................................................................................................................... 1
研究動機 ...................................................................................................................................... 1
相關研究 ...................................................................................................................................... 3
1-2-1 場列式可程式類比陣列(FPAA) ............................................................................................ 3
1-2-2 可程式化類比元件陣列(PANDA) ........................................................................................ 4
論文結構 ...................................................................................................................................... 6
第二章、背景知識 ............................................................................................................................ 7
波動數位濾波器背景知識 ........................................................................................................... 7
2-1-1 波動數位濾波器模型 .......................................................................................................... 7
2-1-2 波動數位濾波器的配線器架構 ........................................................................................ 10
採用WDF 理論的類比電路仿真流程 ....................................................................................... 12
自動建構WDF 樹狀結構 ........................................................................................................... 14
2-3-1 歪斜WDF 樹狀結構 .......................................................................................................... 15
2-3-2 自動建立WDF 樹狀結構 .................................................................................................. 16
在高階合成中的排程................................................................................................................. 17
第三章、WDF 樹狀結構建立流程 .................................................................................................. 19
WDF 模型轉換建立 .................................................................................................................... 20
3-1-1 WDF 元件對映 .................................................................................................................... 20
3-1-2 場效電晶體分割 ................................................................................................................ 22
電路分析 .................................................................................................................................... 23
3-2-1 電路元件堆疊層級編號分析 ............................................................................................ 24
3-2-2 配線器插入 ........................................................................................................................ 25
3-2-3 完全合併並聯電路交換 .................................................................................................... 28
3-2-4 配線器拓樸 ........................................................................................................................ 29
3-2-5 瓶頸狀況處理 .................................................................................................................... 30
WDF 樹狀結構建立與優化 ......................................................................................................... 33
3-3-1 WDF 樹狀結構優化 ............................................................................................................ 33
3-3-2 動態建立WDF 樹狀結構 .................................................................................................. 34
WDF 排程 .................................................................................................................................... 36
3-4-1 WDF 配線器延遲時間 ........................................................................................................ 37
3-4-2 WDF 樹狀結構排程限制 .................................................................................................... 38
3-4-3 展開WDF 樹狀結構 .......................................................................................................... 39
3-4-4 配線器撥散排程法 ............................................................................................................ 41
第四章、實驗結果 .......................................................................................................................... 44
一階差動放大器 ........................................................................................................................ 44
RLC 電路 ...................................................................................................................................... 47
4-2-1 RLC 傳輸線排程前後差異 .................................................................................................. 47
4-2-2 RLC 傳輸線長度不同結果 .................................................................................................. 48
第五章、結論 .................................................................................................................................. 51
參考文獻 ......................................................................................................................................... 52

參考文獻

[1] G. E. Moore, “Cramming More Components Onto Integrated Circuits,” Proceedings of the IEEE, Jan 1998.
[2] G. Richard, “Analog/Mixed-Signal Behavioral Modeling - When to Use What,” Cadence Design Communities, Feb 2011.
[3] E. K. F. Lee & P. G. Gulak, “A CMOS field-programmable analog array,” IEEE Journal of Solid-State Circuits, pp. 1860-1867, Dec 1991.
[4] E. K. F. Lee & P. G. Gulak, “MOS Transconductor-Based Field-Programmable Analog Array,” Solid-State Circuits Conference, 1995.
[5] H. Kutuk, & S.-M. Kang, “A field-programmable analog array (FPAA) using switched-capacitor techniques,” Circuits and Systems, 1996. ISCAS 96., Connecting the World., 1996 IEEE International Symposium on, pp. 41-44 vol.4, May 1996.
[6] N. Suda & J. Suh & N. Hakim & Y. Cao & B. Bakkaloglu, “A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation,” IEEE transactions on Circuits and Systems I: Regular Papers, pp. 181-190, Jan 2016.53
[7] A. Fettweis, “Wave digital filters: Theory and practice”.
[8] K. Meerkotter & R. Scholz, “Digital simulation of nonlinear circuits by wave digital filter principles,” IEEE Int’l Symp. on Circuits and Systems,, pp. 720-
723, 1989.
[9] Y.-S. Han, “A Simulation Platform for Analog Circuits Using Wave Digital Filters and Nonlinear MOS Model,” M.S. thesis, Central University, Taiwan, 2015.
[10] C . Yeh, “Timing and Resource Optimization of Pipelined Analog Emulator Based on Wave Digital Filters,” M.S. thesis, Central University, Taiwan, 2015.
[11] B .-H. Tsai, “Automatic Construction of Wave Digital Filter Structure for Analog Circuit Emulation,” M.S. thesis, Central University, Taiwan, 2015.
[12] W . Wu, & Y.-L. Chen, & Y. Ma, & C.-N. J. Liu, & J.-Y. Jou, & S. Pamarti, & L.He, “Wave Digital Filter based Analog Circuit Emulation on FPGA,” in Proc. Int’l Symp. on Circuits and Systems,, May 2016.
[13] R . J. &. M. J. V. Singh, “A Wave Digital Filter Three-Port Adaptor with fine grained pipelining,” Application Specific Array Processors, 1991. Proceedings of the International Conference on, pp. 116-128, Sep. 1991.
[14] S . Ogrenci Memik & E. Bozorgzadeh & R. Kastner & M. Sarrafzadeh, “A super-scheduler for embedded reconfigurable systems,” Nov. 2001. 54
[15] W . S. &. Z. J. Mong, “Register pressure aware scheduling for high level synthesis,” 16th Asia and South Pacific Design Automation Conference, pp.461-466, Jan 2011.
[16] F . R. Awwad & M. Nekili, “Regeneration techniques for RLC VLSI interconnects,” Microelectronics, 2001. ICM 2001 Proceedings.The 13th International Conference on, pp. 209-212, Oct. 2011.
[17] R . Zheng & J. Suh & C. Xu & N. Hakim & B. Bakkaloglu & Y. Cao, “Programmable analog device array (PANDA): A platform for transistor-level analog reconfigurability,” Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 322-327, June 2011.

指導教授

劉建男

審核日期

2016-8-17

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