博碩士論文 103521052 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:3 、訪客IP:34.204.183.113
姓名 劉為劭(Wei-Shao Liu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 空乏型功率金屬氧化物半導體場效電晶體 設計、模擬與特性分析
(Design, Simulation and Analysis of Depletion-mode Power MOSFET)
相關論文
★ 電子式基因序列偵測晶片之原型★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 以標準CMOS製程實現之850 nm矽光檢測器★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計
★ 具有低摻雜P型緩衝層與穿透型P+射源結構之600V穿透式絕緣閘雙極性電晶體★ 雙閘極金氧半場效電晶體與電路應用
★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析★ 氮化鎵電晶體 SPICE 模型建立 與反向導通特性分析
★ 加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討
★ 離子佈植砷化鎵金屬半導體場效電晶體之研究★ 碰撞游離係數的量測及其在異質接面雙極性電晶體之設計應用
★ 磷化銦鎵/砷化鎵異質接面雙極性電晶體之研製及其集極調變對元件特性的影響★ 砷化鎵基體異質接面雙極性電晶體之研製與其在積體化功率放大器之應用
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 本論文針對目標額定崩潰電壓為150 V與閘極臨界電壓為-5 V之空乏型功率金屬氧化物半導體場效電晶體(Depletion-mode Power MOSFET)進行設計、製作流程模擬與測量結果分析。藉由模擬結果討論製程條件對元件的影響,以及製程條件之穩定度探討。使用的製程模擬軟體是TCAD,實際製程是在6吋的矽晶圓上完成。邊緣終端區的最佳化設計過程分成三個方向做崩潰電壓與邊緣終端區結構的分析:改變保護環(guard ring)之數量、主動區(active area)相對於第一個保護環之間距,以及場板(field plate)之有無,其最終結果崩潰電壓可達到150 V以上,以配合主動區之設計。本研究成功製作出崩潰電壓達171 V,閘極臨界電壓-5.56 V之元件。
此外,比較模擬結果與實際製作之元件量測數據,經由適當校正後萃取得到元件相關電性及物理參數,建構其等效電路之HSpice模型並使用適當的動靜態測電路,進行元件導通、耐壓、電容的特性模擬與分析比較,以便能夠在應用電路的模擬中使用。
摘要(英) This research demonstrated the design, analysis, simulation, and characterization of a depletion-mode Power MOSFET with the rated breakdown voltage of 150 V and threshold voltage of -5 V. Impacts of different process conditions on both breakdown voltages and threshold voltages have been discussed and investigated by the simulation using TCAD software. Process sensitivity was also taken account to match the real situation. Devices fabrication were performed on 6-inch silicon wafer and some of them were packaged in SOT-23 form. Moreover, the edge termination was discussed and simulated with considerations in number of guard rings, distance from active area to 1st guard ring and effect of field plate. The optimized design of termination showed breakdown voltage over 150 V, which met the target of active area region.
By comparison of simulation results and measurement data, the electrical and physical parameters of MOSFET were extracted via appropriate procedure. An equivalent circuit for HSPICE model was proposed and combined with test circuits to demonstrate the performance of fabricated MOSFET. The simulation using proposed equivalent circuit includes the characteristics of conduction, breakdown and capacitance have been accomplished.
Using TCAD device process/characteristics simulator and HSPICE circuit software to fully describe the characteristics of this device and bring an appropriate equivalent model so that application circuit design can be implemented successfully.
關鍵字(中) ★ 空乏型功率金屬氧化物半導體場效電晶體
★ 空乏型
★ 閘極臨界電壓
★ 等效電路模型
關鍵字(英) ★ Depletion-mode Power MOSFET
★ Depletion-mode
★ threshold voltage
★ equivalent model
論文目次 摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章 功率場效電晶體簡介 4
2.1 前言 4
2.2 功率元件之結構發展 4
2.3 空乏型功率場效電晶體介紹與應用 6
2.4 空乏型功率場效電晶體操作原理 8
2.5 空乏型功率場效電晶體的重要參數 12
2.6 結論 27
第三章 150V空乏型功率場效電晶體製程模擬與分析 28
3.1 前言 28
3.2 元件設計目標 28
3.3 空乏型功率場效電晶體製造流程 29
3.3.1 製造流程參數對元件影響 31
3.4 空乏型功率場效電晶體特性與分析 32
3.4.1 空乏型功率場效電晶體靜態特性模擬與實驗結果 32
3.4.2 空乏型功率場效電晶體動態特性模擬與實驗結果 45
3.5 邊緣終端區(Edge Termination)設計與分析 50
3.5.1 邊緣終端區之設計 50
3.5.2 邊緣終端區之製作流程 51
3.5.3 邊緣終端區之特性模擬 52
3.6 結論 59
第四章 空乏型功率場效電晶體之等效電路SPICE模型建立與模擬分析 60
4.1 前言 60
4.2 空乏型功率場效電晶體等效模型 60
4.2.1 空乏型功率場效電晶體等效電路模型建立 61
4.2.2 空乏型功率場效電晶體等效電路模型參數萃取 63
4.3 空乏型功率場效電晶體模擬電路 66
4.3.1 導通特性 66
4.3.2 耐壓特性 67
4.3.3 電容特性 68
4.4 結論 72
第五章 總結與未來展望 73
參考文獻 74
參考文獻 [1] 山崎浩, “Power MOSFET 應用技術,” 全華科技圖書股份有限公司, 2004。
[2] Antoine A. Tamer, Ken Rauch, and John L. Moll, “Numerical Comparison of DMOS, VMOS, and UMOS Power Transistors,” IEEE Transactions on Electron Devices, vol. ED-30, No. 1, January. 1983.
[3] Mohamed N. Darwish, “Study of the Quasi-Saturation Effect in VDMOS Transistors,” IEEE Transactions on Electron Devices, vol. ED-33, No. 11, Nov. 1986.
[4] Hitoshi Yamaguchi, Naohiro Suzuki and Jun Sakakibara, “Ultra Low On-resistance Super 3D MOSFET,” International Symposium on Power Semiconductor Devices & IC′s (ISPSD), Cambridge, UK, Apr. 2003.
[5] Kondekar Pravin N, “Analytical Design and Simulation Studies of Super-junction Power MOSFET,” IEEE International Symposium on Industrial Electronics (ISIE), pp.503-508, June, 2007.
[6] Ying Wang, Hai-fan Hu, Chao Cheng, “Simulation study of semi-superjunction power MOSFET with SiGe pillar,” Superlattices and Microstructures, vol. 47, no. 2, pp. 314–324, Feb, 2010.
[7] Bill Chen, “Depletion-Mode MOSFET: The Forgotten FET,” Supertex Inc, Sunnyvale, CA, Application Notes, AN-D66, 2013.
[8] Hong Lin, “Market and Technology Trends in WBG Power Module Packaging,” Power Conversion, Intelligent Motion (PCIM), Shanghai, June. 2015, pp.8.
[9] 簡鳳佐, “功率電子專刊I,” 台灣電子材料與元件協會, pp.5-6, VOL. 20, NO.1, 2014。
[10] B.J. Baliga, “Trends in Power Semiconductor Devices,” IEEE Transactions On Electron Devices, Vol. 43, No. 10, October 1996.
[11] Roger Valtonen, Jörgen Olsson and Peter De Wolf, “Channel Length Extraction for DMOS Transistors Using Capacitance-Voltage Measurements,” IEEE Transactions on Electron Devices, Vol. 48, No. 7, July 2001.
[12] B.J. Baliga, Fundamentals of Power Semiconductor Devices. Springer, pp 279-291, 2008.
[13] 董正暉, “功率電晶體低導通電阻及高頻化之改良研究,” 逢甲大學資訊電機工程碩士在職專班論文, 2005。
[14] V. A. K. Temple and P. Y. Gray, "Theoretical comparison of DMOS and VMOS structures for voltage and on-resistance", IEDM Tech. Dig., pp. 88-93, 1979
[15] Wang Cailin, Sun Cheng, “A new shallow trench and planar gate MOSFET structure based on VDMOS technology,” Journal of Semiconductors, Volume 32, Number 2, 2011.
[16] Raghavendra S. Saxena and M. Jagadesh Kumar, “Trench Gate Power MOSFET: Recent Advances and Innovations,” Advances in Microelectronics and Photonics, Chapter 1, Nova Science Publishers, Inc. 400 Oser Avenue, Suite 1600, Hauppauge, NY 11788, USA, pp:1-23, 2012.
[17] Pradeep Kumar Tamma, “Applications for Depletion MOSFET,” Infineon Technologies AG, Munich, Germany, Application Notes, AN_201410_PL11_003, Feb. 2015.
[18] Linden Harrison, “An introduction to Depletion-mode MOSFETs.” Available: http://www.aldinc.com/pdf/IntroDepletionModeMOSFET.pdf
[19] Sachin Seth, “Compact Modeling Concerns for Silicon-based Power MOSFETs,” EEWeb Magazines, May. 2014. Available: https://www.eeweb.com/blog/sachin_seth/compact-modeling-concerns-for-silicon-based-power-mosfets
[20] 林毓誠, “600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計,” 國立中央大學電機工程學系碩士論文, 2011。
[21] B.J. Baliga, Power Semiconductor Devices. PWS Publishing Company, Boston, MA, pp 398-401, 1995.
[22] B.J. Baliga, Fundamentals of Power Semiconductor Devices. Springer, pp 327-329, 2008.
[23] William P. Robbins, “Power MOSFETs,” Department of Electrical and Computer Engineering , University of Minnesota, Lecture Notes, Available: http://aboutme.samexent.com/classes/spring09/ee5741/MOSFETs.pdf
[24] ON Semiconductor, “MOSFET Gate-Charge Origin and its Applications,” ON Semiconductor Corp, Colorado, USA, Application Notes, AND9083/D, rev. 2, Feb, 2016.
指導教授 辛裕明(Yue-Ming Hsin) 審核日期 2016-8-30
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明