參考文獻 |
[1] Committee, I.R., "International Technology Roadmap for Semiconductors, " 2013
Edition. Semiconductor Industry Association.
[2] Iwai, H., “Future of Logic Nano CMOS Technology,” IEEE EDS DL, IIT-Bombay,Jan. 2015.
[3] Wang, P.-F., K. Hilsenbeck, Th. Nirschl, M. Oswald, Ch. Stepper, M. Weis, D. Schmitt-Landsiedel, W. Hansch, "Complementary tunneling transistor for low power application."Solid-State Electronics, 48(12): p. 2281-2286. 2004.
[4] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect
transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec” ,IEEE
Electron Device Letters, vol. 28, no. 8, pp. 743-745, August, 2007.
[5] Mookerjea, S. and Datta, S., “Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic
Applications,” IEEE Device Research Conf., Santa Barbara, CA, Jun. 2008, pp.
47-48.
[6] Mookerjea, S., Mohata,D., Krishnan R., Singh J., Vallet A., Ali A., Mayer T., Narayanan V., Schlom D., Liu A. and Datta S., “Experimental demonstration of 100nm channel length In0.53Ga0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications,” IEEE Electron Devices Meeting (IEDM), Baltimore, MD, Dec. 2009, pp. 1-3.
[7] Mookerjea, S., Mohata, D., Mayer, T., Narayanan, V. and Datta, S., “Temperature-Dependent I–V Characteristics of a Vertical In0.53Ga0.47As Tunnel FET,” IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-566, Jun. 2010.
[8] Yan Zhu, Mohata, D.K., Datta, S. and Hudait, M.K., “Reliability Studies on High-Temperature Operation of Mixed As/Sb Staggered Gap Tunnel FET Material andDevices,” IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 245-254, Mar. 2014.
[9] Han Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, and J. Lee, "Tunneling Field-Effect Transistors With an of 50 and a Subthreshold Swing of 86 mV/dec Using Gate Oxide."Electron Device Letters, 31(12): p. 1392-1394.2010.
[10] Rui Li, Yeqing Lu, Guangle Zhou, Qingmin Liu, Soo Doo Chae, Tim Vasen, Wan Sik Hwang, Qin Zhang and Patrick Fay, “AlGaSb/InAs Tunnel Field-Effect Transistor With On-Current of 78 μA/μm at 0.5 V,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 363-365, Mar. 2012.
[11] Tao Yu, James T., Dimitri A. and Judy L., "In0. 53Ga0. 47As/GaAs0. 5Sb0. 5 Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics." Electron Device Letters, 34(12): p. 1503-1505.2013
[12] Ritesh Jhaveri, Venkatagirish Nagavarapu and Jason C. S. Woo, "Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor." IEEE Transactions on Electron Devices, vol. 58, no. 1, Jan. 2011
[13] Yasuhiro Utsumi, "Transistor statistics add up Better predictions of electron behavior could reduce the size of computer chips. " Riken Research, Jun. 2016
[14] S.M. Sze and K.K. Ng, Physics of Semiconductor Devices, 3rd ed. Canada: John Wiley & Sons, Inc., 2007, ch.8.
[15] D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. M. Fastenau, D. Loubychev, A. K. Liu and S. Datta, "Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications." IEEE Electron Devices Meeting (IEDM), Washington, DC, Dec. 2011, pp. 33.5.1 - 33.5.4
[16] D. K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu, T. S. Mayer, V. Narayanan and S. Datta, “Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio,” IEEE VLSI Technology (VLSIT), Honolulu, HI, Jun. 2012, pp. 53-54.
[17] Dheeraj Mohata, Bijesh Rajamohanan, Theresa Mayer, Mantu Hudait, Dmitri Lubyshev, Amy W. K. Liu and Suman Datta, “Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1568-1570, Nov. 2012.
[18] R. Bijesh, H. Liu, H. Madan, D. Mohata, W. Li1 , N. V. Nguyen , D. Gundlach , C.A. Richter , J. Maier, K. Wang, T. Clarke, J. M. Fastenau , D. Loubychev , W. K. Liu , V. Narayanan and S. Datta, “Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 Near Broken-gap Tunnel FET with ION=740μA/μm, GM=700μS/μm and Gigahertz Switching Performance at VDS=0.5V,” IEEE Electron Devices Meeting (IEDM), Washington, DC, Dec. 2013, pp. 28.2.1-28.2.4.
[19] G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu, D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljevic, H. W. Then and R. Chau “Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing,” IEEE Electron Devices Meeting (IEDM), Washington, DC, Dec. 2011, pp. 33.6.1-33.6.4. |