| 摘要(英) |
The second generation digital satellite broadcasting (DVB-S2) is a new generation of digital satellite broadcasting standards to enhance the transmission relative to DVB-S. In the channel coding, the LDPC code is used as the inner code, the BCH code is used as the outer code, and the two error correction codes are combined to provide good error correction capability, and the LDPC code has two code lengths, as well as various code rates, Different needs.
In this thesis,we design and implementation of DVB-S2 Transmitter with SDR Platform,including BCH code, LDPC code, Bit interleaver and modulator. This paper is based on the existing DVB-S2 specification to be integrated, and the laboratory supply of FPGA and AD9361 for realtime presentation.In order to achieve real time we must calculate the throughput rate of each code rate and symbol rate, after all the code rate throughput and symbol rate calculation, this paper decided to LDPC encoding parallel input coding, this method can reduce the multiples of the encoding time to make Throughput can be improved. The integrated transmitter of this thesis can be used to control the signal transmission by simple parameters to achieve high-volume DVB-S2 transmitter.
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| 參考文獻 |
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