博碩士論文 103523003 詳細資訊




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姓名 毛聖博(Sheng-Po Mao)  查詢紙本館藏   畢業系所 通訊工程學系
論文名稱 以軟體定義無線電平台設計與實現DVB-S2發射機
(Design and Implementation of DVB-S2 Transmitter with SDR Platform)
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摘要(中) 第二代數位衛星廣播 (DVB-S2) 為新一代的數位衛星廣播標準以提升相較於 DVB-S之傳輸量。在通道編碼方面,使用LDPC碼作為內碼,BCH碼作為外碼,用兩種錯誤更正碼組合,提供良好的錯誤更正能力,且LDPC碼兩種碼長,以及各種碼率,可使用在不同需求。

本論文研究內容以軟體定義無線電實現DVB-S2發射端,包含BCH碼,LDPC碼,Bit interleaver和調變器。本論文將現有的DVB-S2規格書加以整合實現,並以FPGA(AC701)和AD9361作realtime呈現。在實現設計中因為硬體最高速度的限制下,實現real time需加以計算每個碼率的throughput 和 symbol rate,經過所有 code rate的throughput 和 symbol rate計算後 ,決定將LDPC編碼採平行輸入編碼,此方式可減少倍數的編碼時間使throughput 能夠提升。而整合系統的部分,因為兩種編碼的碼率多樣性,使得為了節省硬體資源必須將編碼器以良好的參數設計方式設計,並且要考量架構種類以便硬體上的實現。本論文所整合的發射機可藉由簡易的參數入控制所需要發射訊號以實現高資料量的DVB-S2發射機。
摘要(英) The second generation digital satellite broadcasting (DVB-S2) is a new generation of digital satellite broadcasting standards to enhance the transmission relative to DVB-S. In the channel coding, the LDPC code is used as the inner code, the BCH code is used as the outer code, and the two error correction codes are combined to provide good error correction capability, and the LDPC code has two code lengths, as well as various code rates, Different needs.

In this thesis,we design and implementation of DVB-S2 Transmitter with SDR Platform,including BCH code, LDPC code, Bit interleaver and modulator. This paper is based on the existing DVB-S2 specification to be integrated, and the laboratory supply of FPGA and AD9361 for realtime presentation.In order to achieve real time we must calculate the throughput rate of each code rate and symbol rate, after all the code rate throughput and symbol rate calculation, this paper decided to LDPC encoding parallel input coding, this method can reduce the multiples of the encoding time to make Throughput can be improved. The integrated transmitter of this thesis can be used to control the signal transmission by simple parameters to achieve high-volume DVB-S2 transmitter.
關鍵字(中) ★ 第二代數位電視廣播
★ LDPC碼
★ BCH碼
★ 通道編碼
★ 平行編碼
關鍵字(英) ★ DVB-S2
★ LDPC encoder
★ BCH encoder
★ channel encoding
★ arallel architecture
論文目次 一 緒論...................1
1.1 研究動機與背景......1
1.2 章節介紹............2
二 DVB-S2規格介紹..........3
2.1 DVB-S2傳送端流程....3
2.2 Frame架構..........4
2.3 Frame內部建構運作...7
三 BCH code...............12
3.1 BCH碼介紹......... 12
3.2 BCH編碼架構........12
四 LDPC code............. 18
4.1 LDPC介紹.......... 18
4.2 DVB-S2之LDPC實現方法18
五 Bit Interleaver........31
5.1 Bit Interleaver介紹31
5.2 Bit Interleaver模組32
5.3 Constellation Mapping35
六 PLHEADER...............36
6.1 PLHEADER架構.......38
6.2 PLHEADER模組.......38
七 Square Root Raise Cosin39
7.1 介紹...............39
7.2 SRRC模組...........42
7.3 SRRC架構...........43
八 On Air實現結果..........44
8.1 軟體定義無線電......44
8.2 結果...............46
九 結論....................51
參考文獻................52
參考文獻 [1] Eroz, Mustafa, Feng?Wen Sun, and Lin?Nan Lee. "DVB?S2 low density parity check codes with near Shannon limit performance." International Journal of Satellite Communications and Networking 22.3 (2004): 269-279.
[2] Morello, Alberto, and Vittoria Mignone. "DVB-S2: The second generation standard for satellite broad-band services." Proceedings of the IEEE 94.1 (2006): 210-227.
[3] Morello, Alberto, and Ulrich Reimers. "DVB?S2, the second generation standard for satellite broadcasting and unicasting." International Journal of Satellite Communications and Networking 22.3 (2004): 249-268.
[4] Thorpe, Jeremy. "Low-density parity-check (LDPC) codes constructed from protographs." IPN progress report 42.154 (2003): 42-154.
[5] Fan, John L. "Array codes as LDPC codes." Constrained Coding and Soft Iterative Decoding (2001): 195-203.
[6] Zhong, Hao, and Tong Zhang. "Block-LDPC: A practical LDPC coding system design approach." IEEE Transactions on Circuits and Systems I: Regular Papers 52.4 (2005): 766-775.
[7] Hong, Eon-Young, Jung-pil Choi, and Youn-Ok Park. "Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method." U.S. Patent No. 8,190,967. 29 May 2012.
[8] Kim, Seok-Min, Chang-Soo Park, and Sun-Young Hwang. "A novel partially parallel architecture for high-throughput LDPC decoder for DVB-S2." IEEE Transactions on Consumer Electronics 56.2 (2010).
[9] Urard, P., et al. "A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes." Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International. IEEE, 2005.
[10] Gunnam, Kiran K., Gwan S. Choi, and Mark B. Yeary. "A parallel VLSI architecture for layered decoding for array LDPC codes." VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on. IEEE, 2007.
[11] Liu, Shi-Cheng, and Shinfeng D. Lin. "BCH code-based robust audio watermarking in the cepstrum domain." Journal of Information Science and Engineering 22.3 (2006): 535-543.
[12] Seki, K., et al. "Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems." Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003. IEEE, 2003.
指導教授 陳逸民(Yih-Min-Chen) 審核日期 2017-4-10
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