||The second generation digital satellite broadcasting (DVB-S2) is a new generation of digital satellite broadcasting standards to enhance the transmission relative to DVB-S. In the channel coding, the LDPC code is used as the inner code, the BCH code is used as the outer code, and the two error correction codes are combined to provide good error correction capability, and the LDPC code has two code lengths, as well as various code rates, Different needs.|
In this thesis,we design and implementation of DVB-S2 Transmitter with SDR Platform,including BCH code, LDPC code, Bit interleaver and modulator. This paper is based on the existing DVB-S2 specification to be integrated, and the laboratory supply of FPGA and AD9361 for realtime presentation.In order to achieve real time we must calculate the throughput rate of each code rate and symbol rate, after all the code rate throughput and symbol rate calculation, this paper decided to LDPC encoding parallel input coding, this method can reduce the multiples of the encoding time to make Throughput can be improved. The integrated transmitter of this thesis can be used to control the signal transmission by simple parameters to achieve high-volume DVB-S2 transmitter.
|| Eroz, Mustafa, Feng?Wen Sun, and Lin?Nan Lee. "DVB?S2 low density parity check codes with near Shannon limit performance." International Journal of Satellite Communications and Networking 22.3 (2004): 269-279.|
 Morello, Alberto, and Vittoria Mignone. "DVB-S2: The second generation standard for satellite broad-band services." Proceedings of the IEEE 94.1 (2006): 210-227.
 Morello, Alberto, and Ulrich Reimers. "DVB?S2, the second generation standard for satellite broadcasting and unicasting." International Journal of Satellite Communications and Networking 22.3 (2004): 249-268.
 Thorpe, Jeremy. "Low-density parity-check (LDPC) codes constructed from protographs." IPN progress report 42.154 (2003): 42-154.
 Fan, John L. "Array codes as LDPC codes." Constrained Coding and Soft Iterative Decoding (2001): 195-203.
 Zhong, Hao, and Tong Zhang. "Block-LDPC: A practical LDPC coding system design approach." IEEE Transactions on Circuits and Systems I: Regular Papers 52.4 (2005): 766-775.
 Hong, Eon-Young, Jung-pil Choi, and Youn-Ok Park. "Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method." U.S. Patent No. 8,190,967. 29 May 2012.
 Kim, Seok-Min, Chang-Soo Park, and Sun-Young Hwang. "A novel partially parallel architecture for high-throughput LDPC decoder for DVB-S2." IEEE Transactions on Consumer Electronics 56.2 (2010).
 Urard, P., et al. "A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes." Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International. IEEE, 2005.
 Gunnam, Kiran K., Gwan S. Choi, and Mark B. Yeary. "A parallel VLSI architecture for layered decoding for array LDPC codes." VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on. IEEE, 2007.
 Liu, Shi-Cheng, and Shinfeng D. Lin. "BCH code-based robust audio watermarking in the cepstrum domain." Journal of Information Science and Engineering 22.3 (2006): 535-543.
 Seki, K., et al. "Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems." Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003. IEEE, 2003.