用於高壓積體電路佈局最佳化的三階B*-Trees

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李致緯(Chih-Wei Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於高壓積體電路佈局最佳化的三階B*-Trees
(Three-Level Hierarchical B*-Trees for Layout Optimization of High-Voltage VLSI Circuits)

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摘要(中)

現今類比電路設計大多以人工的方式產生佈局，雖然使用類比設計自動化工具可以節省設計工作量，但類比電路眾多的佈局限制仍是類比設計自動化發展的難題。目前存在許多類比元件擺置的相關文獻，然而對於高壓電路晶片擺置的研究卻非常稀少。高壓電路在設計與佈局上的限制都較為複雜，且操作電壓較高且廣，為確保連接高電壓與低電壓等。不同電壓的電晶體於操作過程中不會受到彼此的干擾，電晶體周圍會使用隔離環（isolation ring）包覆以達到保護元件的效果，但是隔離環於電路佈局時卻占大量的面積，有必要開發適當的擺置最佳化演算法，以降低下線成本。考量高壓類比電路的敏感性，於佈局最佳化面積的同時也必須考慮其元件擺置的對稱性及可繞線度等限制，如此更增加高壓類比電路佈局自動化的困難度。
本論文提出一個在擺置階段考量高壓類比電路對稱性及其佈局限制的最佳化流程。擺置過程中，會先以P-Cell的方式分析元件的擺放限制與大小，根據萃取到的資訊，在考慮電晶體對稱的條件下不斷地改變電晶體層級及隔離環（isolation ring）層級的擺放位置，藉由改變電晶體的位置使隔離環改變面積及形狀後，再改變隔離環位置使整體面積降至最小。從實驗結果來看，透過演算法擺置元件後，其於節省面積與程式執行的效率都有很不錯的表現。

摘要(英)

Currently, the layouts of analog circuits are often generated manually. Although some EDA tools can help to reduce design efforts, the complexity of layout constraints is still a big issue that limits the development of EDA tools. In the literature, there are many works related to the placement of analog circuits. However, few of them are discussing about the placement of high-voltage circuits. Compared with general circuits, the design of high-voltage circuits is more complex with more constraints. Since high-voltage circuits demand higher operating voltages and wider voltage ranges, transistors often require isolation rings around them to protect transistors from disturbing each other. Because isolation rings will occupy large chip area, it is necessary to develop proper EDA tools for the placement optimization with isolation rings to reduce the chip cost. Due to the sensitivity of high-voltage circuits, some additional constraints such as symmetry and routability should be considered during placement stage, which further increases the difficulties of EDA tools.
This thesis proposes a placement flow to consider both symmetry constraints and isolation rings for the placement optimization of high-voltage circuits. First, we analyze the size and constraints of the P-cell elements in the original circuits. Following the extracted constraints, we will adjust the location of transistors inside every isolation rings to change the shape of isolation rings. Meanwhile, different shapes of isolation rings will be considered simultaneously during the placement algorithm to optimize the layout area. According to the experimental results, the proposed placement algorithm is able to reduce the chip area for high-voltage designs with isolation rings and still keeps the algorithm efficiency.

關鍵字(中)

★ 高壓電路
★ 自動化佈局

關鍵字(英)

★ High-Voltage Circuits
★ automatic placement
★ B*-Trees

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
第一章、緒論 1
1-1 類比電路設計自動化 1
1-2 研究動機 3
1-3 問題定義 5
1-4 論文結構 6
第二章、背景知識 7
2-1 類比電路擺置考量 7
2-1-1 匹配 7
2-1-2 對稱 8
2-1-3 鄰近 9
2-2 高壓類比電路 10
2-2-1 高壓類比電路元件 10
2-2-2 高壓類比電路佈局 11
2-3 類比電路擺置的演算法 12
2-3-1 B*-Trees 13
2-3-2 階級式B*-Trees 14
第三章、演算法流程 23
3-1 隔離環擺置與鄰近擺置 24
3-2 佈局元件資料萃取 24
3-3 樹狀結構 25
3-3-1 隔離環層級二元樹 27
3-4 模擬退火演算法 32
3-4-1 樹狀架構的變換機制 33
3-4-2 階級式B*-Trees的變換限制 33
3-4-3 邊界節點的變換 35
3-4-4 成本函數 36
第四章、實驗結果及分析 38
4-1 實驗環境 38
4-2 實驗電路 39
4-3 實驗結果數據及佈局圖 46
第五章、結論與未來展望 54
參考文獻 55

參考文獻

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[2]Juergen Scheible and Jens Lienig, “Automation of Analog IC Layout-Challenges and Solutions,” Proc. International Symposium on Physical Design, pp. 33-40, 2015.
[3]Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, and Shu-Wei Wu, “B*-Trees: A New Representation for Non-Slicing Floorplans,” Proc. Design Automation Conference, pages 458-463, 2000.
[4]Po-Hung Lin, Yao-Wen Chang, and Shyh-Chang Lin, “Analog Placement Based on Symmetry-Island Formulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 791-804, June 2009.
[5]Po-Hung Lin and Shyh-Chang Lin, “Analog Placement Based on Hierarchical Module Clustering,” Proc. Design Automation Conference, pp. 50–55, 2008.
[6]黃弘一, “Ch03-Analog Layout Consideration,” 混合訊號積體電路佈局與分析課程講義, Jan.2001.
[7]Michael Eick, Martin Strasser, Helmut E. Graeb, and Ulf Schlichtmann, “Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits, ” Proc. International Symposium on Physical Design, pp. 14–17, 2010.
[8]Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, and Wei-Zen Chen, “Fast Analog Layout Prototyping for Nanometer Design Migration,” Proc. International Conference Computer –Aided Design, pp. 517–522, 2011.
[9] Mark Po-Hung Lin, Bo-Hao Chiang, Jen-Chieh Chang, Yu-Chang Wu, Rong-Guey Chang, Shuenn-Yuh Lee, “Augmenting Slicing Trees for Analog Placement,” Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012.
[10]Scott Kirkpatrick,Charles Daniel Gelatt, and Mario Pietro Vecchi, “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671–680, May 1983.
[11]Po-Hung Lin and Shyh-Chang Lin, “Analog placement based on novel symmetry-island formulation,” Proc. Design Automation Conference, pp. 465–470, 2007.
[12]Juergen Scheible and Jens Lienig, “Automation of Analog IC Layout-Challenges and Solutions,” Proc. International Symposium on Physical Design, pp. 33-40, 2015.
[13]Tsung-Yu Liu, “Reliability-Driven Placement for Analog Integrated Circuits,” M.S. thesis, Central University, Taiwan, 2015.
[14]Yiu-cheong Tam, Evangeline F. y. Young, Chris Chu, “Analog Placement with Symmetry and Other Placement Constraints,” Proc. International Conference Computer-Aided Design, pp.349-354, 2006
[15]Rui He, Lihong Zhang, “Analog placement design with constraints of multiple symmetry groups”, Proc. Electrical and Computer Engineering, pp. 1204-1207, 2009.

指導教授

劉建男、夏勤(Chien-Nan Liu Chin Hsia)

審核日期

2016-8-23

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