博碩士論文 104521016 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:13 、訪客IP:54.234.0.2
姓名 駱祈宏(Chi-Hung Lo)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 基於高壓製程的高速位準轉換器設計
(High speed level shifter design based on high voltage BCD process)
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檔案 [Endnote RIS 格式]    [Bibtex 格式]    至系統瀏覽論文 (2022-7-31以後開放)
摘要(中) 本論文基於栓鎖式電壓位準轉換電路提出兩種新型適用於高電壓位準轉換器電路架構,並使用高壓製程中的功率電晶體作為電壓隔離器件設計電路。由於功率元件當作高壓隔離開關切換時存在米勒平台效應造成延遲,因此本論文提出利用電阻負載式以及電阻負載稽納二極體式兩種高壓位準轉換器結構,希冀能增加電壓位準轉換的速度。另外,為了解高壓製程中DPW_NBL隔絕環是否在不同逆向偏壓時對轉換器性能造成的影響,在電路中低壓區域的N+深埋層以及高壓區域的N+深埋層分別施以相同以及不同的電壓值以探討差異。為驗正本文提出的位準轉換器架構性能,本論文分別設計並量測三種不同結構的電壓轉換上升電路以電壓轉換下降電路,其中使用TSMC 0.25-um 60-V Bipolar-CMOS-DMOS(BCD) 高壓製程實現高電壓位準轉換器,最後比較轉換器性能以及建立效能指數(FOM)分析。文中所設計的電壓轉換上升位準轉換器可將輸入信號0到5V電壓,頻率為5MHz方波平移為正20V到正25V的方波,總共用於分析比較的七組轉換器整體晶片面積為2603 um X 611um;而電壓轉換下降位準轉換器可將輸入信號0到5V電壓,頻率為5MHz的方波平移為負20V到負25V的方波,7組轉換器整體晶片面積為2595.7 um X 649.4um。
摘要(英) Two novel level-shifter architectures based on cross-coupled latch pairs for high voltage level-shifter applications was proposed and analyzed in this thesis. Since high votlage power transistors were employed as isolated protection devcies inside the level shifters, and the delay caused by Miller effect exists while power transistors switch on and off, two different high voltage level shilfters with resisitive loading and zener diode in series with a resistor, respectively, were designed to increase the transtion speed of the level shifters. In addition, to understand the roles of DPW_NBL isolated ring of the high votlage process while different reverse bias votlage applied with and effects on the performance of the level shifters, the N+ deep burried layer in the low voltage region and the high voltage region, respectively, were applied with the same and different voltage levels, separately, to examine the effects. In order to verify the proposed architectures, three kinds of different high voltage level shifters, including level-shifting from low voltage to high voltage, and high voltage to low voltage, were designed using TSMC 0.25um 60V Bipolar-CMOS-DMOS (BCD) process. The performance matrix (Figure of merit) was built and analyzed. The designed 7 different level-shifter circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a 20 ~ 25V square wave occupy total area of 2603um x 611um, and the other 7 circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a -20 ~ -25V square wave occupy the area of 2595.7um x 649.4um, respectively.
關鍵字(中) ★ 位準轉換器設計
★ 整合式雙極性/互補金氧半元件/擴散式金氧半元件
★ N+深埋層
關鍵字(英) ★ level-shifter
★ Bipolar-CMOS-DMOS
★ N-buried Layer
論文目次 摘要ii
Abstract iii
誌謝v
目錄vi
圖目錄 xii
表目錄 xviii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 4
第二章 高壓BCD製程暨元件介紹 5
2.1 BCD製程介紹 5
2.1.1 BCD種類 7
2.1.2 元件隔離技術 11
2.1.2.1 自我絕緣技術 11
2.1.2.2 接面絕緣技術 12
2.1.2.3 介電質絕緣技術 13
2.2 元件介紹 14
2.2.1 N型橫向擴散金屬氧化物半導體架構 15
2.2.2 P型橫向擴散金屬氧化物半導體架構 17
第三章 高壓位準轉換器架構 19
3.1 電阻負載稽納二極體式高壓上升位準轉換器 19
3.2 高壓上升位準轉換器結構 24
3.2.1 主動式箝位高壓上升位準轉換器 26
3.2.2 電阻負載式高壓上升位準轉換器 30
3.2.3 快速低功耗高壓上升位準轉換器 32
3.3 總結 34
第四章 高壓高速位準轉換器設計 35
4.1 高壓上升位準轉換器設計 35
4.1.1 主動式箝位高壓上升位準轉換器 35
4.1.2 電阻負載式高壓上升位準轉換器 38
4.1.3 電阻負載稽納二極體式高壓上升位準轉換器 41
4.2 高壓下降位準轉換器設計 45
4.2.1 主動式箝位高壓下降位準轉換器 45
4.2.2 電阻負載式高壓下降位準轉換器 48
4.2.3 電阻負載稽納二極體式高壓下降位準轉換器 51
4.3 接面絕緣技術(電壓測試) 55
第五章 高壓高速位準轉換器模擬 57
5.1 高壓上升位準轉換器結構(前模擬不包含寄生電容) 58
5.1.1 主動式箝位高壓上升位準轉換器 58
5.1.1.1 相同N+深埋層電壓以及包含ESD 59
5.1.1.2 不相同N+深埋層電壓以及包含ESD 62
5.1.2 電阻負載式高壓上升位準轉換器 65
5.1.2.1 相同N+深埋層電壓以及包含ESD 66
5.1.2.2 不相同N+深埋層電壓以及包含ESD 69
5.1.3 電阻負載稽納二極體式高壓上升位準轉換器 72
5.1.3.1 相同N+深埋層電壓以及包含ESD 73
5.1.3.2 不相同N+深埋層電壓以及包含ESD 76
5.1.3.3 不相同N+深埋層電壓以及不包含ESD 79
5.1.4 電路表現分析 82
5.2 高壓下降位準轉換器結構(前模擬不包含寄生電容) 85
5.2.1 主動式箝位高壓下降位準轉換器 85
5.2.1.1 相同N+深埋層電壓以及包含ESD 86
5.2.1.2 不相同N+深埋層電壓以及包含ESD 89
5.2.2 電阻負載式高壓下降位準轉換器 92
5.2.2.1 相同N+深埋層電壓以及包含ESD 93
5.2.2.2 不相同N+深埋層電壓以及包含ESD 96
5.2.3 電阻負載稽納二極體式高壓下降位準轉換器 99
5.2.3.1 相同N+深埋層電壓以及包含ESD 100
5.2.3.2 不相同N+深埋層電壓以及包含ESD 103
5.2.3.3 不相同N+深埋層電壓以及不包含ESD 106
5.2.4 電路表現分析 109
5.3 高壓上升位準轉換器結構(後模擬包含寄生電容電阻) 112
5.3.1 主動式箝位高壓上升位準轉換器 112
5.3.1.1 相同N+深埋層電壓以及包含ESD 113
5.3.1.2 不相同N+深埋層電壓以及包含ESD 116
5.3.2 電阻負載式高壓上升位準轉換器 119
5.3.2.1 相同N+深埋層電壓以及包含ESD 120
5.3.2.2 不相同N+深埋層電壓以及包含ESD 123
5.3.3 電阻負載稽納二極體式高壓上升位準轉換器 126
5.3.3.1 相同N+深埋層電壓以及包含ESD 127
5.3.3.2 不相同N+深埋層電壓以及包含ESD 130
5.3.3.3 不相同N+深埋層電壓以及不包含ESD 133
5.3.4 電路表現分析 136
5.4 高壓下降位準轉換器結構(後模擬包含寄生電容電阻) 139
5.4.1 主動式箝位高壓下降位準轉換器 139
5.4.1.1 相同N+深埋層電壓以及包含ESD 140
5.4.1.2 不相同N+深埋層電壓以及包含ESD 143
5.4.2 電阻負載式高壓下降位準轉換器 146
5.4.2.1 相同N+深埋層電壓以及包含ESD 147
5.4.2.2 不相同N+深埋層電壓以及包含ESD 150
5.4.3 電阻負載稽納二極體式高壓下降位準轉換器 153
5.4.3.1 相同N+深埋層電壓以及包含ESD 154
5.4.3.2 不相同N+深埋層電壓以及包含ESD 157
5.4.3.3 不相同N+深埋層電壓以及不包含ESD 160
5.4.4 電路表現分析 163
5.5 規格比較 166
5.5.1 高壓上升位準轉換器結構 167
5.5.2 高壓下降位準轉換器結構 169
第六章 晶片佈局與量測考量 171
6.1 晶片佈局 171
6.1.1 晶片封裝 173
6.1.2 佈局規劃 175
6.2 晶片照相與量測環境設定 175
6.3 高壓上升位準轉換器結構(量測結果) 178
6.3.1 主動式箝位高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 178
6.3.2 主動式箝位高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 180
6.3.3 主動式箝位高壓上升位準轉換器比較 182
6.3.4 電阻負載式高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 183
6.3.5 電阻負載式高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 185
6.3.6 電阻負載式高壓上升位準轉換器比較 187
6.3.7 電阻負載稽納二極體式高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 188
6.3.8 電阻負載稽納二極體式高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 190
6.3.9 電阻負載稽納二極體式高壓上升位準轉換器不相同N+深埋層電壓以及不包含ESD 192
6.3.10 電阻負載稽納二極體式高壓上升位準轉換器比較 194
6.4 高壓下降位準轉換器結構(量測結果) 195
6.4.1 主動式箝位高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 195
6.4.2 主動式箝位高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 197
6.4.3 主動式箝位高壓下降位準轉換器比較 199
6.4.4 電阻負載式高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 200
6.4.5 電阻負載式高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 202
6.4.6 電阻負載式高壓下降位準轉換器比較 204
6.4.7 電阻負載稽納二極體式高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 205
6.4.8 電阻負載稽納二極體式高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 207
6.4.9 電阻負載稽納二極體式高壓下降位準轉換器不相同N+深埋層電壓以及不包含ESD 209
6.4.10 電阻負載稽納二極體式高壓下降位準轉換器 比較 211
6.5 規格比較 212
6.5.1 高壓上升位準轉換器結構 213
6.5.2 高壓下降位準轉換器結構 215
第七章結論與未來研究方向 217
參考文獻 218
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指導教授 夏勤(Chin Hsia) 審核日期 2017-8-24
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