鍺與砷化銦鎵鰭式場效電晶體共閘極製程之開發

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姓名

許乃蓉(Nai-Rong Hsu) 查詢紙本館藏

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電機工程學系

論文名稱

鍺與砷化銦鎵鰭式場效電晶體共閘極製程之開發
(Development of a Common Gate-Stack Process for Ge and InGaAs Fin Field-Effect Transistors)

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摘要(中)

隨著積體電路技術的快速發展與進步，製程技術逐漸接近物理極限，需要找尋新的可行性且接受度大的通道材料來突破此困境，根據產業技術發展現況判斷，鍺的電洞遷移率為矽的數倍，所以被認為很可能是未來金氧半場效電晶體的P型通道材料，而N型通道材料則可能會由具有高電子遷移率的III-V族砷化物擔綱。然而，要實現異質整合之鍺與砷化銦鎵互補式金氧半電晶體，必須先解決目前高介電常數材料與半導體界面缺陷重多的問題。而兩者相較，又以鍺之閘極製程較為成熟與穩定，因此，本研究以鍺之閘極製程為基礎，提出一種新穎的半導體表面處理方法，可同時適用於奈米級鍺與砷化銦鎵鰭式場效電晶體之製作，以利鍺與砷化銦鎵互補式金氧半電晶體之整合。
本研究是以原子層沉積法成長的氧化鋁作為高介電常數材料，首先以電容的特性來評估此製程之可行性，其製作方式為將鍺與砷化銦鎵磊晶片經化學溶液清潔、熱氧化處理以及電漿處理後，立即沉積氧化鋁於其上。所製作的氧化鋁/(鍺，砷化銦鎵)電容特性顯示，在室溫下的調變率分別為55%和72%，以電導法估計界面補陷密度，前者在價電帶附近的界面補陷密度為7.85×1011 eV-1cm-2，後者在導電帶附近的界面補陷密度約為2.58×1011 eV-1cm-2，顯示氮氣電漿處理可同時有效降低二者之界面捕陷。後續之實驗顯示，氮氣電漿處理亦可以提升元件之熱穩定性。氧化鋁/(鍺，砷化銦鎵)電容經550oC快速熱退火後，砷化銦鎵電容在累積區之頻散現象從3.4%/dec減小至2.5%/dec，鍺電容之調變從72%提升至83%而頻散現象也從1.47%/dec減少至0.94%/dec。這些結果證實此共閘極製程技術應用於鍺與砷化銦鎵金氧半電晶體之可行性。
在確認上述共閘極製程參數之後，吾人即以此技術製作鍺與砷化銦鎵無接面(junctionless)鰭式場效電晶體。其中，鍺通道層材料是以低壓化學氣相沉積法成長於Silicon on Insulator (SOI)基板上；砷化銦鎵通道層材料則是以分子束磊晶法成長於以磷化銦基板之砷化銦鋁緩衝層上。鰭式場效電晶體是以電子束微影系統進行鰭式通道與閘極區域的定義，其中Ge pFinFET與InGaAs nFinFET之閘極長度與鰭通道寬度分別為 80 nm/30 nm與 40 nm/60 nm。以此閘極製程同時製作之鍺與砷化銦鎵鰭式場效電晶體均具有電晶體之調變特性，其開關電流比分別為104與103，最大汲極電流密度分別為60 µA/µm與2 µA/µm，次臨界擺幅分別為180 mV/dec與384 mV/dec，且其閘極漏電流均低於10-4 µA/µm。雖然砷化銦鎵鰭式場效電晶體之汲極電流密度因通道過度蝕刻而過小，此研究已初步顯示此共閘極製程在未來積體電路製造之應用潛力。

摘要(英)

Following the rapid development of integrated circuit technology, the quest for integrating high-mobility channel metal-oxide-semiconductor field-effect transistors (MOSFETs) has become even more urgent because current aggressively scaled devices are approaching their physical limit. As indicated by the recent status of material technology, Ge, which has higher hole mobility than Si, is likely to be the choice for p-channel MOSFETs, while high electron mobility III-V materials, such as InGaAs, could be used for the n-channel MOSFETs. However, to realize the integrated Ge and InGaAs CMOS scheme, one has to cope with the complex structure and composition of the native oxides of Ge and InGaAs, which result in defect states at the oxide-semiconductor interface. Since the gate-stack process of Ge MOS, which involves rapid thermal oxidation (RTO), is a rather mature process, this work is devoted to the development of a common gate-stack process based on this process so that it can be used to fabricate Ge and InGaAs fin field effect transistors (FinFETs) simultaneously.
In this study, Al2O3 prepared by atomic layer deposition (ALD) is used as a high dielectric constant material. The feasibility of this common gate-stack process is evaluated based on the characteristics of Ge and InGaAs metal-oxide-semiconductor capacitors (MOSCAPs). The Ge and InGaAs epilayers were chemically cleaned in an HF solution and subjected to a RTO process. Then, the samples were treated by nitrogen plasma right before the deposition of the Al2O3 gate dielectric. Post metal annealing (PMA) was performed to reduce the oxide traps and the border traps near the oxide-semiconductor interface. The Ge and InGaAs MOSCAPs prepared by the nitrogen plasma treatment show effective capacitance modulations of 55% and 72%, respectively. Their interface trap density is 7.85×1011 eV-1cm-2 near the valence band, and 2.58×1011 eV-1cm-2 near the conduction band, respectively, as extracted by the conductance method. It indicates that nitrogen plasma treatment can effectively decrease interface traps in both InGaAs and Ge MOSCAPs. A series heating experiments shows that nitrogen plasma treatment can also improve the thermal stability of MOSCAPs. After rapid thermal annealing at 550°C, the dispersion of CV curves in accumulation region decreases from 3.4%/dec to 2.5%/dec for the InGaAs MOSCAP and from 1.47%/dec to 0.94%/dec for the Ge MOSCAP. In addition, the Ge MOSCAP’s modulation improves from 72% to 83%.
After confirming the common gate process parameters, the proposed gate-stack process was used to fabricate junctionless (Ge,InGaAs) FinFETs. The Ge channel layer material was grown on a silicon-on- insulator (SOI) substrate by low pressure chemical vapor deposition, and the InGaAs channel layer material was grown on an InP substrate with an InAlAs buffer layer by molecular beam epitaxy (MBE). The gate length (Lg) and fin width (Wfin) of the Ge pFinFET and InGaAs nFinFET prepared by electron beam exposure are 80 nm/30 nm and 40 nm/60 nm, respectively. The Ge and InGaAs FinFETs exhibit Ion/Ioff ratio of 104 and 103, subthreshold swing of 180 mV/de and 384 mV/dec, and maximum drain current of 60 µA/µm and 2 µA/µm, respectively. The gate leakage current for both the Ge and InGaAs FinFETs is below 10-4 µA/µm. Although the drain current density of the InGaAs FinFETs is unexpectedly small, which may be due to over etching, this work has demonstrated the feasibility of this common gate process for Ge/InGaAs CMOS integrated circuits.

關鍵字(中)

★ 共閘極
★ 鍺
★ 砷化銦鎵
★ 鰭式場效電晶體

關鍵字(英)

★ Common gate
★ Ge
★ InGaAs
★ FinFET

論文目次

摘要 I
Abstract III
目錄 VI
圖目錄 VIII
表目錄 X
第一章緒論 1
1.1 前言 1
1.2 研究動機 3
1.2.1 材料選擇 3
1.2.2 氧化層/半導體界面缺陷 6
1.2.3 鰭式場效電晶體優點 9
1.3 論文架構 11
第二章理論基礎與實驗設備 12
2.1 前言 12
2.2 金屬-氧化物-半導體電容之物理特性 13
2.3 介電層/半導體界面分析方法與原理 17
2.3.1 氧化層/半導體界面缺陷種類介紹 17
2.3.2 介面缺陷密度計算及分布 20
2.4 實驗儀器 24
2.4.1 原子層沉積系統簡介 24
2.4.2 原子力顯微鏡簡介 26
2.4.3 X-射線光電子能譜系統簡介 29
第三章高溫電漿表面處理後對共閘極氧化鋁/鍺與砷化銦鎵金氧半電容
之研究 30
3.1 簡介 30
3.2 試片製備與實驗步驟 32
3.3 界面處理條件對鍺與砷化銦鎵金氧半電容電性變化之探討 35
3.3.1 高溫氮氣電漿處理對金氧半電容影響之分析 35
3.3.2 金氧半電容熱穩定性之探討 40
3.4 電漿處理後氧化鋁/鍺與砷化銦鎵表面形貌分析 42
3.5 具氮氣電漿處理共閘極氧化鋁/鍺與砷化銦鎵之界面分析 44
3.5.1 界面缺陷密度計算與能帶分布 44
3.5.2 氧化層/半導體界面化合物探討 47
3.6 本章總結 49
第四章鍺與砷化銦鎵鰭式場效電晶體製作及特性分析 51
4.1 前言 51
4.2 鍺鰭式場效電晶體製程技術開發 52
4.2.1 製作流程 52
4.2.2 定義鍺鰭式通道及蝕刻形貌 56
4.3 砷化銦鎵鰭式場效電晶體製程技術開發 58
4.3.1 製作流程 58
4.3.2 定義砷化銦鎵鰭式通道及蝕刻形貌 64
4.4 鰭式場效電晶體特性分析與討論 66
4.4.1 鍺與砷化銦鎵鰭式場效電晶體之電氣特性探討 66
4.4.2 鍺與砷化銦鎵鰭式場效電晶體之高解析 TEM 圖 68
4.5 本章總結 69
第五章總結 70
參考文獻 71

參考文獻

[1] S. Takagi, M. Noguchi, M. Kim, S. H. Kim, C. Y. Chang, M. Yokoyama, et al., ”III-V/Ge MOS device technologies for low power integrated systems,” Solid-State Electronics, vol. 125, p. 82, 2016.
[2] N.-T. Yeh, P.-C. Chiu, J.-I. Chyi, F. Ren, and S. J. Pearton, ”Sb-based semiconductors for low power electronics,” Journal of Materials Chemistry C, vol. 1, p. 4616, 2013.
[3] R. Suzuki, N. Taoka, M. Yokoyama, S. Lee, S. H. Kim, T. Hoshii, et al., ”1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density,” Applied Physics Letters, vol. 100, p. 132906, 2012.
[4] T. D. Lin, W. H. Chang, R. L. Chu, Y. C. Chang, Y. H. Chang, M. Y. Lee, et al., ”High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors by in-situ atomic-layer-deposited HfO2,” Applied Physics Letters, vol. 103, p. 253509, 2013.
[5] R. Zhang, P.-C. Huang, J.-C. Lin, N. Taoka, M. Takenaka, and S. Takagi, ”High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Postoxidation,” IEEE Transactions on Electron Devices vol. 60, p. 927, 2013.
[6] D. Lin, G. Brammertz, S. Sioncke, C. Fleischmann, A. Delabie, K. Martens, et al., ”Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution,” Electron Devices Meeting (IEDM), 2009 IEEE International, p. 1, 2009.
[7] W. C. Lee, P. Chang, T. D. Lin, L. K. Chu, H. C. Chiu, J. Kwo, et al., ”InGaAs and Ge MOSFETs with high κ dielectrics,” Microelectronic Engineering, vol. 88, p. 336, 2011.
[8] C. H. Fu, Y. H. Lin, W. C. Lee, T. D. Lin, R. L. Chu, L. K. Chu, et al., ”Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process,” Microelectronic Engineering, vol. 147, p. 330, 2015.
[9] 謝承軒, ”氧化鋁/砷化銦鰭式場效電晶體之製作與特性分析,” 國立中央大學, 2014.
[10] E. H. Nicollian and A. Goetzberger, ”The Si-SiO2 interface---Electrical properties as determined by the metal-insulator-silicon conductance technique,” Bell System Technology Journal, vol. 46, p. 1055, 1967.
[11] 徐賢名, ”氧化鉿 /氧化鋁 /銻化鎵金氧半結構製備與界面缺陷分析,” 國立中央大學, 2014.
[12] 許哲瑋, ”氧化鉿∕砷化銦金氧半結構之製備及其介面與電性研究,” 國立中央大學, 2012.
[13] R. Engel-Herbert, Y. Hwang, and S. Stemmer, ”Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces,” Journal of Applied Physics, vol. 108, p. 124101, 2010.
[14] G. Binnig, C. F. Quate, and C. Gerber, ”Atomic force microscope,” Phys Rev Lett, vol. 56, p. 930, Mar 03 1986.
[15] J. Thornton, ”Scanning Probe Microscopy Training Notebook,” ed: version, 2000.
[16] P. Bhatt, K. Chaudhuri, S. Kothari, A. Nainani, and S. Lodha, ”Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation,” Applied Physics Letters, vol. 103, p. 172107, 2013.
[17] S. Stemmer, V. Chobpattana, and S. Rajan, ”Frequency dispersion in III-V metal-oxide-semiconductor capacitors,” Applied Physics Letters, vol. 100, p. 233510, 2012.
[18] Y. Yuan, L. Wang, and B. Yu, ”A Distributed Model for Border Traps in Al2O3/InGaAs MOS Devices,” IEEE Electron Device Letters, vol. 32, p. 485, 2011.
[19] P. Goley and M. Hudait, ”Germanium Based Field-Effect Transistors: Challenges and Opportunities,” Materials, vol. 7, p. 2301, 2014.
[20] L. K. Chu, C. Merckling, A. Alian, J. Dekoster, J. Kwo, M. Hong, et al., ”Low interfacial trap density and sub-nm equivalent oxide thickness in In0.53Ga0.47As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO2/Al2O3 as gate dielectrics,” Applied Physics Letters, vol. 99, p. 042908, 2011.
[21] C. H. Wang, S. W. Wang, G. Doornbos, G. Astromskas, K. Bhuwalka, R. Contreras-Guerrero, et al., ”InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces,” Applied Physics Letters, vol. 103, p. 143510, 2013.
[22] P. D. C. King, T. D. Veal, H. Lu, S. A. Hatfield, W. J. Schaff, and C. F. McConville, ”The influence of conduction band plasmons on core-level photoemission spectra of InN,” Surface Science, vol. 602, p. 871, 2008.
[23] T. Hoshii, M. Yokoyama, H. Yamada, M. Hata, T. Yasuda, M. Takenaka, et al., ”Impact of InGaAs surface nitridation on interface properties of InGaAs metal-oxide-semiconductor capacitors using electron cyclotron resonance plasma sputtering SiO2,” Applied Physics Letters, vol. 97, p. 132102, 2010.
[24] P. Motamedi and K. Cadien, ”XPS analysis of AlN thin films deposited by plasma enhanced atomic layer deposition,” Applied Surface Science, vol. 315, p. 104, 2014.
[25] S.-H. Hsu, C.-L. Chu, and G.-L. Luo, ”Selective dry-etching process for fabricating Ge gate-all-around field-effect transistors on Si substrates,” Thin Solid Films, vol. 540, p. 183, 2013.

指導教授

綦振瀛(Jen-Inn Chyi)

審核日期

2017-8-21

推文