參考文獻 |
[1] N. Waldron, C. Merckling, W. Guo, P. Ong, L. Teugels, S. Ansar, et al., "An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates," in VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, pp. 1-2, 2014.
[2] C.-H. Jan, "10 years of transistor innovations in System-on-Chip (SoC) era," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on, pp. 1-4, 2014.
[3] C.-H. Jan, P. Bai, J. Choi, G. Curello, S. Jacobs, J. Jeong, et al., "A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp. 60-63, 2005.
[4] C.-H. Jan, P. Bai, S. Biswas, M. Buehler, Z.-P. Chen, G. Curello, et al., "A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors," in Electron Devices Meeting, 2008. IEEE International, pp. 1-4, 2008.
[5] P. VanDerVoorn, M. Agostinelli, S.-J. Choi, G. Curello, H. Deshpande, M. El-Tanani, et al., "A 32nm low power RF CMOS SOC technology featuring high-k/metal gate," in VLSI Technology (VLSIT), 2010 Symposium on, pp. 137-138, 2010.
[6] C.-H. Jan, U. Bhattacharya, R. Brain, S.-J. Choi, G. Curello, G. Gupta, et al., "A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications," in Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 3.1. 1-3.1. 4, 2012.
[7] S. Novak, C. Parker, D. Becher, M. Liu, M. Agostinelli, M. Chahal, et al., "Transistor aging and reliability in 14nm tri-gate technology," in Reliability Physics Symposium (IRPS), 2015 IEEE International, pp. 2F. 2.1-2F. 2.5, 2015.
[8] C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, et al., "A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Inte rconnects," in Electron Devices Meeting (IEDM), 2017 IEEE International, pp. 29.1. 1-29.1. 4, 2017.
[9] S. Takagi, S. H. Kim, M. Yokoyama, R. Zhang, N. Taoka, Y. Urabe, et al., "High mobility CMOS technologies using III–V/Ge channels on Si platform," Solid-State Electronics, vol. 88, pp. 2-8, 2013.
[10] D. J. Smith, J. Lu, T. Aoki, M. R. McCartney, and Y.-H. Zhang, "Observation of compound semiconductors and heterovalent interfaces using aberration-corrected scanning transmission electron microscopy," Journal of Materials Research, vol. 32, pp. 921-927, 2016.
[11] J.-W. Wu, C.-Y. Chang, K.-C. Lin, E. Y. Chang, J.-S. Chen, and C.-T. Lee, "The thermal stability of ohmic contact to n-type InGaAs layer," Journal of electronic materials, vol. 24, pp. 79-82, 1995.
[12] R. Dormaier and S. E. Mohney, "Factors controlling the resistance of Ohmic contacts to n-InGaAs," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 30, p. 031209, 2012.
[13] J. Lee, M. Li, J. Kim, G. Shin, G.-w. Lee, J. Oh, et al., "Contact Resistance Reduction between Ni–InGaAs and n-InGaAs via Rapid Thermal Annealing in Hydrogen Atmosphere," JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 17, pp. 283-287, 2017.
[14] S. Kim, M. Yokoyama, R. Nakane, O. Ichikawa, T. Osada, M. Hata, et al., "High-performance InAs-on-insulator n-MOSFETs with Ni-InGaAs S/D realized by contact resistance reduction technology," IEEE Transactions on Electron Devices, vol. 60, pp. 3342-3350, 2013.
[15] A. K. Baraskar, M. A. Wistey, V. Jain, U. Singisetti, G. Burek, B. J. Thibeault, et al., "Ultralow resistance, nonalloyed Ohmic contacts to n-In Ga As," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 27, pp. 2036-2039, 2009.
[16] A. M. Crook, E. Lind, Z. Griffith, M. J. Rodwell, J. D. Zimmerman, A. C. Gossard, et al., "Low resistance, nonalloyed Ohmic contacts to InGaAs," Applied Physics Letters, vol. 91, p. 192114, 2007.
[17] E. H. Rhoderick, "Metal-semiconductor contacts," IEE Proceedings I-Solid-State and Electron Devices, vol. 129, p. 1, 1982.
[18] S. M. Sze and K. K. Ng, Physics of semiconductor devices: John wiley & sons, 2006.
[19] A. Yu, "Electron tunneling and contact resistance of metal-silicon contact barriers," Solid-State Electronics, vol. 13, pp. 239-247, 1970.
[20] C.-Y. Chang, Y.-K. Fang, and S. M. Sze, "Specific contact resistance of metal-semiconductor barriers," Solid-State Electronics, vol. 14, pp. 541-550, 1971.
[21] T. Shen, G. Gao, and H. Morkoc, "Recent developments in ohmic contacts for III–V compound semiconductors," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 10, pp. 2113-2132, 1992.
[22] S. S. Li, "Metal–semiconductor contacts," in Semiconductor Physical Electronics, ed: Springer, pp. 284-333, 2006.
[23] T. Suntola, "Atomic layer epitaxy," Materials Science Reports, vol. 4, pp. 261-312, 1989.
[24] 許宏泰、徐英展、陳志立、謝明勳, "高解析度穿透式電子顯微鏡分析(HRTEM)," 國立台灣大學化學系.
[25] 張銀祐, "掃瞄式電子顯微鏡及能量散佈光譜儀原理與奈米科技應用," 2007.
[26] D. Vaughan, "Energy Dispersive X-ray Microanalysis An Introduction," Thermo Fisher Scientific Inc., 2008.
[27] D. Ivey, "Platinum metals in ohmic contacts to III-V semiconductors," Platinum Metals Review, vol. 43, pp. 2-12, 1999.
[28] C.-T. Lee, K.-L. Jaw, and C.-D. Tsai, "Thermal stability of Ti/Pt/Au ohmic contacts on InAs/graded InGaAs layers," Solid-State Electronics, vol. 42, pp. 871-875, 1998.
[29] T. Shen, Z. Fan, G. Gao, H. Morkoc, and A. Rockett, "Molecular‐beam‐epitaxy‐deposited nonalloyed Al contacts to n‐type and p‐type InGaAs," Applied physics letters, vol. 59, pp. 2254-2256, 1991.
[30] 許乃蓉, "鍺與砷化銦鎵鰭式場效電晶體共閘極製程之開發," 國立中央大學, 2017.
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