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姓名 林峻緯(Chun-Wei Lin) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 複合式通道穿隧式場效電晶體
(Heterojunction Tunnel Field-Effect Transistors with Composite Channel)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 有別於金氧半場效電晶體利用擴散機制，次臨限擺幅受限於kT/q的影響，穿隧式場效電晶體是藉由載子在能帶間穿隧來產生電流，因此在常溫下次臨限擺幅可以突破60 mV/decade的限制。以III-V族材料製作穿隧式場效電晶體相較矽基材料具有較低的材料能隙得以改善導通電流不足的問題，再進一步的利用異質的結構可以在接面處形成更小的等效穿隧能障來獲得更大的導通電流，卻也因為載子更容易的在接面處發生穿隧，導致電晶體在關閉狀態下有漏電流增加的問題。
本論文提出一創新複合式通道設計，針對銻砷化鎵/砷化銦鎵穿隧式場效電晶體在靠近汲極端通道的地方加入一層高能隙的銻砷化鎵材料形成一新穎的複合式通道的穿隧式場效電晶體，改善銻砷化鎵/砷化銦鎵異質結構穿隧式場效電晶體漏電流的問題，並維持相同的導通電流，得到高Ion/Ioff的特性以及更小的次臨限擺幅。所使用的傳統磊晶為p+-i-n+摻雜的銻砷化鎵/砷化銦鎵異質結構，源極為p+銻砷化鎵，摻雜碳元素，電洞濃度大於5 × 1019 cm-3，砷的莫耳比例為51%，銻的莫耳比例為49%；汲極為n+砷化銦鎵，摻雜矽元素，電子濃度大於1 × 1018 cm-3，銦的莫耳比例為53%，鎵的莫耳比例為47%，而複合式通道i層為銻砷化鎵/砷化銦鎵組合，厚度分別為120 / 30 nm。
藉由Silvaco Atlas模擬，與傳統銻砷化鎵/砷化銦鎵穿隧式場效電晶體比較，新複合式通道穿隧式場效電晶體之漏電流可以改善約5個數量級，並將雙極性導通效應和導通電壓之差異從0.110 V提高為0.331 V。在導通的狀態下，由於閘極偏壓下傳輸通道i層能帶下拉的關係，使得發生穿隧的載子不需要跨過高能隙的銻砷化鎵，可以同時得到高的導通電流，進一步得到更高的電流開關比。在無閘極二極體元件模擬結果中，可觀察到以複合式通道結構的二極體有較高的漏電流，必需搭配閘極偏壓控制複合式通道i層才能有效降低漏電流，符合穿隧式場效電晶體之運作。
利用MBE成長三種磊晶片，先製作無閘極二極體元件，複合式通道結構的二極體與銻砷化鎵/砷化銦鎵異質磊晶二極體及具砷化銦鎵口袋式銻砷化鎵/砷化銦鎵異質磊晶二極體進行電性比較。複合式通道結構的二極體之順偏狀態電流相對傳統結構上升約三個數量級，而逆偏狀態電流，下降約一個數量級，趨勢如模擬所呈現。再藉由光學曝光與先乾蝕刻再濕蝕刻的方式成功製作出微米尺寸的複合式通道穿隧式場效電晶體，先乾蝕刻再濕蝕刻的方式主要為了克服溼蝕刻對兩層不同材料的通道層的蝕刻速率不同所導致的通道控制能力不佳的問題。室溫條件下，複合式通道穿隧式場效電晶體的最小關閉電流可達5.43 × 10-6 µA/µm，電流開關比為23.20，最佳次臨限擺幅為190 mV/decade。歸因於複合式通道的設計，元件的關閉電流非常小，可應用於超低功耗的應用。不過導通電流及電流開關比未能如模擬的高值，主要原因是通道的銻砷化鎵層控制不完全，如要進一步改善斜面蝕刻控制，必須找到對銻砷化鎵及砷化銦鎵複合式通道蝕刻速率相近的蝕刻溶液或是乾蝕刻條件來改善得到最佳的閘極控制。摘要(英)
In traditional metal oxide semiconductor field effect transistors (MOSFETs), subthreshold swing (S.S.) is limited by kT/q (60 mV/dec) because of drift-diffusion carriers in the channel. However, the band-to-band tunneling current in tunnel field effect transistors (TFETs) is able to improve S.S. to be less than 60 mV/decade at room temperature. Compared with the Silicon based TFETs, the on-state current in III-V materials based TFETs can be increased due to higher tunneling probability from narrow and direct band gaps. Further using hetero-structure in the source side can reduce effective tunneling barrier height to induce higher on-state current. However, carriers may easily tunnel through the source side junction and cause the high leakage current in the off-state and ambipolar conduction.
In this study, we propose GaAsSb/InGaAs hetero-junction TFET with a novel composite channel. A high bandgap GaAsSb material is inserted near drain side channel and formed a composite channel. The proposed TFETs can improve the problem of leakage current and maintain the high on-state currents, thus higher Ion/Ioff and better S.S. can be obtained. The basic structure of TFETs in this study is a p+-i-n+ GaAsSb/InGaAs/InGaAs epitaxial layers. Sourse material is a heavy doped p+-GaAsSb. Drain material is a heavy doped n+-InGaAs. The composite channel material is a combination of 120-nm GaAsSb and 30-nm InGaAs layer..
By Silvaco Atlas simulation, compared with traditional GaAsSb/InGaAs TFET, the novel composite channel TFET shows leakage current can be reduced by five orders of magnitude, and ambipolar conduction is reduced. In on-state bias, the composite channel TFET demonstrates the same high on-state currents compared to GaAsSb/InGaAs hetero-junction TFET due to the same tunneling junction at the source side though higher gate voltage is required to reduce the blocking effect from GaAsSb in the channel. Therefore, higher on/off current ratio (Ion/Ioff) is observed.
The epitaxial layers of all TFETs were grown by MBE. Device fabrication was started with drain metallization. After that dry etching then wet etching method was used to define and expose the channel region before gate dielectric deposition. The dry etching then wet etching method is to overcome the different etching rate for two different materials in the channel, which results in the channel control ability. At room temperature, the characteristics of composite channel TFET showed the minimum off current (Ioff) of 5.43 × 10-6 µA/µm, the highest on/off current ratio (Ion/Ioff) of 23.20, and the minimum S.S. of 190 mV/decade. Due to the composite channel design, off-state current is redcued. But the on-state current is not as high as the value of simulation. The main reason is the GaAsSb layer in the composite channel is not totally controlled by gate bias. Am improved dry etching technique is required to fabricate device in order to demonstrate the advantages of the proposed TFETs.關鍵字(中) ★ 穿隧式場效電晶體
★ 複合式通道關鍵字(英) ★ Tunnel Field-Effect Transistors
★ Heterojunction
★ Composite Channel論文目次
摘要 I
ABSTRACT III
致謝 V
目錄 VI
圖目錄 VIII
表目錄 XIII
第一章 導論 1
1.1穿隧式場效電晶體研究發展 1
1.2研究動機 25
1.3論文架構 25
第二章 穿隧式場效電晶體電性改善研究 27
2.1 前言 27
2.2穿隧理論與穿隧電流 27
2.3江崎二極體(ESAKI DIODE) 30
2.4穿隧式場效電晶體操作機制 33
2.5穿隧式場效電晶體元件特性的重要參數介紹 35
2.6穿隧式場效電晶體之雙極性導通行為(AMBIPOLAR BEHAVIOR)介紹 36
2.7結論 37
第三章 銻砷化鎵/砷化銦鎵複合式通道穿隧式場效電晶體之設計與模擬分析 38
3.1前言 38
3.2複合式通道穿隧式場效電晶體之設計與操作機制 39
3.2.1電晶體 39
3.2.2無閘極二極體元件操作 45
3.3複合式通道穿隧式場效電晶體之模擬特性分析 49
3.3.1改變通道銻砷化鎵厚度比較 49
3.3.2改變汲極材料摻雜濃度比較 53
3.3.3最佳化閘極金屬功函數 55
3.4結論 56
第四章 銻砷化鎵/砷化銦鎵複合式通道穿隧式場效電晶體之製程與電性分析 58
4.1前言 58
4.2銻砷化鎵/砷化銦鎵複合式通道磊晶結構 58
4.3複合式通道穿隧式場效電晶體製作流程 59
4.3.1無閘極二極體元件 59
4.3.2電晶體 64
4.4複合式通道穿隧式場效電晶體特性與分析 74
4.4.1無閘極二極體元件 75
4.4.2電晶體 84
4.5結論 90
第五章 總結與未來展望 92
參考文獻 94
附錄 乾蝕刻製程與先溼蝕刻後再乾蝕刻製程結果 97參考文獻
[1] Jack Y.-C. Sun, “System Scaling and Collaborative Open Innovation”, VLSI Tech. Symp., pp. T2-T7, Jun. 2013
[2] Iwai, H., “Future of Logic Nano CMOS Technology”, IEEE EDS DL, IIT-Bombay, Jan. 2015.
[3] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as nergy-efficient electronic switches”, Nature, vol. 479, pp. 329-337, Nov. 2011.
[4] Dmitri Nikonov, "Course on Beyond CMOS Computing", https://nanohub.org/resources/18347, Jun. 2013.
[5] Heike Riel, Lars-Erik Wernersson, Minghwei Hong, and Jesús A. del Alamo, “III–V compound semiconductor transistors—from planar to nanowire structures”, Materials Research Society BULLETIN, vol. 39, pp. 668-677, Aug. 2014.
[6] Bill Holt, “Advancing moore’s law”, Intel investor meeting, Santa Clara , Nov. 2015.
[7] Alireza Alian and Aaron Thean from IMEC“Increasing the indium content in the InGaAs channel boosts the drive current of a tunnel FET while maintaining its great switching behaviour”, Compound Semiconductor Magazine, Aug. 2016.
[8] Mookerjea, S. and Datta, S., “Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications”, IEEE Device Research Conf., Santa Barbara, CA, pp. 47-48, Jun. 2008.
[9] S. Mookerjea ; D. Mohata ; R. Krishnan ; J. Singh ; A. Vallett ; A. Ali ; T. Mayer ; V. Narayanan ; D. Schlom ; A. Liu ; S. Datta, “Experimental demonstration of 100nm channel length In0.53Ga0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications”, IEEE International Electron Devices Meeting(IEDM), Baltimore, MD, pp. 1-3, Dec. 2009.
[10] Mookerjea, S., Mohata, D., Mayer, T., Narayanan, V. and Datta, S., “Temperature-Dependent I–V Characteristics of a Vertical In0.53Ga0.47As Tunnel FET”, IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-566, Jun. 2010.
[11] D. K. Mohata ; R. Bijesh ; S. Mujumdar ; C. Eaton ; R. Engel-Herbert ; T. Mayer ; V. Narayanan ; J. M. Fastenau ; D. Loubychev ; A. K. Liu and S. Datta, “Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic application”, IEEE International Electron Devices Meeting (IEDM), Washington, DC, pp. 33.5.1-33.5.4, Dec. 2011.
[12] D. K. Mohata ; R. Bijesh ; S. Mujumdar ; C. Eaton ; R. Engel-Herbert ; T. Mayer ; V. Narayanan ; J. M. Fastenau ; D. Loubychev ; A. K. Liu ; S. Datta, “Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio”, IEEE VLSI Technology (VLSIT), Honolulu, HI, pp. 53-54, Jun. 2012.
[13] Dheeraj Mohata ; Bijesh Rajamohanan ; Theresa Mayer ; Mantu Hudait ; Joel Fastenau ; Dmitri Lubyshev ; Amy W. K. Liu ; Suman Datta, “Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current”, IEEE International Electron Device Letters, vol. 33, no. 11, pp. 1568-1570, Nov. 2012.
[14] R. Bijesh ; H. Liu ; H. Madan ; D. Mohata ; W. Li ; N. V. Nguyen ; D. Gundlach ; C.A. Richter ; J. Maier ; K. Wang ; T. Clarke ; J. M. Fastenau ; D. Loubychev ; W. K. Liu ; V. Narayanan and S. Datta, “Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 NearBroken-gap Tunnel FET with ION=740μA/μm,GM=700μS/μm and Gigahertz Switching Performance at VDS=0.5V”, IEEE International Electron Devices Meeting(IEDM), Washington, DC, pp. 28.2.1-28.2.4, Dec. 2013.
[15] Rajamohanan, B., et al. “0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET,” IEEE Electron Device Letters, vol. 36, no. 1, pp. 20-22, Jan. 2015.
[16] Tejas Krishnamohan ; Donghyun Kim ; Shyam Raghunathan ; Krishna Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope”, IEEE International Electron Devices Meeting(IEDM), San Francisco, CA, Dec. 2008.
[17] Bin Zhao ; Yan Liu ; Hongjuan Wang ; Jing Yan ; Mingshan Liu ; Chunfu Zhang ; Shengdong Hu ; Yue Hao and Genquan Han, “Investigation of Performance Enhancement in InAs/InGaAs Heterojunction-Enhanced N-Channel Tunneling Field Effect Transistor”, Superlattices and Microstructures, vol. 88, pp. 90-98, Dec. 2015.
[18] Xin Zhao, Vardi, A. and del Alamo, J.A., “InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Fabricated by a Top-down Approach,” IEEE International Electron Devices Meeting(IEDM), San Francisco, CA, Dec. 2014, pp. 25.5.1-25.5.4.
[19] Hao Lu and Alan Seabaugh, “Tunnel Field-Effect Transistors: State-of-the-Art”, IEEE Journal of the Electron Devices Society, vol. 2, no. 4, pp. 44-49, July 2014.
[20] S.M. Sze and K.K. Ng, “Physics of Semiconductor Devices”, 3rd ed. Canada: John Wiley & Sons, Inc., ch.8, 2007.
[21] Sze, S.M. and K.K. Ng, “Physics of Semiconductor Devices”, Canada: John Wiley & Sons, 2006.
[22] F. Mayer ; C. Le Royer ; J.-F. Damlencourt ; K. Romanjek ; F. Andrieu ; C. Tabone ; B. Previtali and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance”, in IEEE International Electron Devices Meeting(IEDM), San Francisco, CA, Dec. 2008, pp.1-5.
[23] Tzu-Yu Yu, Chun-Wei Lin, Cheng-Yu Chen, Chao-Min Chang, Jen-Inn Chyi and Yue-Ming Hsin , “Improved On-state Current and Subthreshold Swing of GaAsSb/InGaAs Tunnel Field-Effect Transistor with a Pocket Layer ” International Electron Devices & Materials Symposium (IEDMS), Nov. 2016.指導教授 辛裕明(Yue-Ming Hsin) 審核日期 2017-7-26 推文 plurk
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