博碩士論文 104521076 詳細資訊




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姓名 黃冠霖(Guan-Lin Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 使用矽基製程之低改變率高速寬頻追蹤保持放大器電路
(Low Droop Rate, High Speed Broadband Track-and-Hold Amplifiers Using Silicon Based Technique)
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摘要(中) 本論文主要闡述低改變率高速寬頻追蹤保持放大器電路之研究,第二章主要論述追蹤保持放大器操作原理、重要參數介紹、追蹤鎖定級設計及降頻率取樣應用,論文內容包含設計分析電路,整體電路模擬及量測結果,模擬方面會先以理想元件進行評估,再來則使用全波電磁模擬軟體模擬分析佈局對電路設計之影響。之後為量測結果,其中以小訊號S參數、無失真動態範圍與波形圖為主。
第三章是使用TSMC 40 nm CMOS製程實現之具有時脈緩衝器頻寬為DC ~ 46 GHz追蹤保持放大器,輸入緩衝級採用共閘極放大器,其寄生電容無米勒放大效應,因此電路能達到寬頻效果,輸出緩衝級的部分則是採用共源極放大器來提高整體增益,並搭配電感提升技術提升整體頻寬,在時脈緩衝器部分則是使用分佈式放大器的架構,分佈式放大器具有寬頻及良好的阻抗匹配特性,輸入高功率弦波使得輸出為方波的方式,量測方面,此追蹤保持放大器架構具有DC ~ 41 GHz 3-dB輸入頻寬、49 dBc無失真動態範圍、平均增益約為 -4.8 dB,直流功耗為104.1毫瓦特,改變率為0.35 mV/ps,晶片尺寸為0.8× 0.9 mm2。
第四章為使用TSMC 0.18 μm SiGe製程所實現DC ~ 17 GHz 追蹤保持放大器,此次輸入緩衝級使用分佈式放大器,詳細說明如何挑選電晶體偏壓及尺寸,以及根據增益公式來求得所需要的級數,並利用電感提升技術,使得高頻增益得以提升,輸出緩衝級利用共源極放大器當作基礎,將HBT電晶體作疊接,能進一步提高隔離度,改善改變率。量測方面,此追蹤保持放大器架構具有DC ~ 17 GHz 3-dB輸入頻寬、54.8 dBc無失真動態範圍、平均增益約為 -4.8 dB,直流功耗為180毫瓦特,改變率為0.4 mV/ps,晶片尺寸為1× 1.3 mm2。
第五章為使用TSMC 0.18 μm SiGe製程所實現DC ~ 11 GHz 主從式追蹤保持放大器,此章節為了改善前一章節的改變率,而做了架構上的修改,將前一章節的追蹤保持放大器修改後組成主從式追蹤保持放大器,並利用兩組時脈緩衝器來控制主追蹤保持放大器以及從追蹤保持放大器,此次輸入緩衝級沿用之前分佈式放大器,面積考量下,將級數設定為兩級,重新挑選電晶體偏壓及尺寸,並利用電感提升技術,使得高頻增益得以提升,由於第一級的輸出緩衝級必須接到下ㄧ級的輸入緩衝級,若輸出緩衝級使用疊接放大器,後級偏壓將會過高,無法推動下一級的追蹤保持放大器,於是將疊接放大器修改為共源極放大器。量測方面,此追蹤保持放大器架構具有DC ~ 10 GHz 3-dB輸入頻寬、38.2 dBc無失真動態範圍、平均增益約為 -5 dB,直流功耗為134毫瓦特,改變率為4 μV/ps,晶片尺寸為2.6× 1.8 mm2。
摘要(英) This thesis focus on the design and analysis of the low droop rate, high speed broadband track-and-hold amplifiers. The design goals of the proposed circuits are broadband, low droop rate and low dc power consumption. The circuit design, analysis, simulation, and measurement are completely presented in this thesis, and the discussion and conclusion are also addressed for the future works.
The introduction and design principle of the THA will be presented in Chapter 2. A differential cancellation technique is proposed for the track-and-hold stage to reduce the feedthrough during the hold mode. To avoid charge injection, the dummy transistors are adopted in the track-and-hold stage. At the end of the Chapter 2, undersampling technique will be discussed.
The proposed THA with clock buffer is frabricated using TSMC 40 nm CMOS general purpose process in Chapter 3.The common-gate amplifier is adopted to enhance the bandwidth of THA. Moreover, the common source topology is employed to enhance the gain and bandwidth of the THA. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 41 GHz with small-signal gain of -4.8 dB. The best SFDR is 49 dBc. The total DC power consumption is 104.1 mW, and the droop rate is 0.35 mV/ps.The chip size is 0.8× 0.9 mm2.
The proposed THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 4.The distributed amplifier is adopted to enhance the bandwidth of THA. The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. Moreover, the Cascode topology is employed to enhance the gain and bandwidth of the THA. The Cascode topology can also improve the isolation during the hold mode. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 17 GHz with small-signal gain of -4.8 dB. The best SFDR is 54.8 dBc. The total DC power consumption is 180 mW, and the droop rate is 0.4 mV/ps.The chip size is 1 × 1.3 mm2.
The proposed Master slave THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 5. To improve the droop rate of the THA in Chpater 4, the THA is resimulated and combined as a master slave topology.The distributed amplifier is be changed to two stages, because three stages will cost a lot of size of the chip . The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. Becauce of the dc level is too high for next stage, the cascode topology is changed to common source. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 10 GHz with small-signal gain of -5 dB. The best SFDR is 38.2 dBc. The total DC power consumption is 134 mW, and the droop rate is 4 μV/ps.The chip size is 2.6 × 1.8 mm2.
關鍵字(中) ★ 追蹤鎖定放大器
★ 微波
★ 毫米波
關鍵字(英) ★ Track and hold amplifier
論文目次 摘要 I
Abstract III
目錄 V
圖目錄 VIII
表目錄 XVI
第1章 緒論 1
1.1 研究動機及背景 1
1.2 現況研究及發展 3
1.3 論文貢獻 5
1.4 論文架構 5
第2章 追蹤鎖定級及降頻率取樣介紹 7
2.1 簡介 7
2.1.1追蹤模態及保持模態 7
2.2 設計重點與重要參數介紹 8
2.2.1 擷取時間(Acquisition time, tacq) 9
2.2.2 保持穩定時間(Hold settling time, ths) 9
2.2.3 基底錯誤(Pedestal error) 10
2.2.4 改變率(Droop rate) 10
2.2.5 電荷注入效應(Charge injection) 10
2.2.6 隔離度(Isolation) 11
2.2.7 無失真動態範圍(Spurious-free dynamic range, SFDR) 11
2.3追蹤鎖定級設計 12
2.3.1 基本開關介紹 12
2.3.2 饋通訊號(Feedthrough) 17
2.3.3 雜散電晶體(Dummy transistor) 19
2.3.4 使用差動式消除器(cancellation) 21
2.3.5 無失真動態範圍(SFDR) 27
2.4降頻率取樣介紹 (Undersampling) 29
第3章 使用40 nm CMOS製程具時脈緩衝器頻寬為DC ~ 46 GHz 之追蹤保持放大器 32
3.1 製程簡介 32
3.2 輸入緩衝級設計 32
3.2.1 共閘極放大器(Common gate) 33
3.2.1 電感設計 37
3.2.2 差動架構模擬方法 41
3.2.3 第三諧波失真項(Third harmonic distortion, HD3) 41
3.3 輸出緩衝級設計 44
3.3.1 共源極放大器(Common Source) 44
3.3.2 第三諧波失真項(Third harmonic distortion, HD3) 46
3.4 時脈緩衝器設計 47
3.5 整體電路模擬 52
3.6 電路實作與量測 60
3.7 電路改進 69
3.8 總結 73
第4章 使用0.18 μm SiGe BiCMOS頻寬為DC ~ 17 GHz追蹤保持放大器 75
4.1 製程簡介 75
4.2 輸入緩衝級設計 75
4.2.1增益單元設計 75
4.2.2電感設計及改良 78
4.2.4第三諧波失真項(Third harmonic distortion, HD3) 84
4.3 輸出緩衝級設計 84
4.3.1疊接放大器架構(Cascode topology) 85
4.3.2第三諧波失真項(Third harmonic distortion, HD3) 86
4.4整體電路模擬 87
4.5電路實作與量測 95
4.6總結 102
第5章 使用0.18 μm SiGe BiCMOS製程頻寬為DC ~ 11 GHz主從式追蹤保持放大器 104
5.1降低改變率之架構論述 104
5.2輸入緩衝級設計 106
5.2.1增益單元設計 106
5.2.2第三諧波失真項(Third harmonic distortion, HD3) 109
5.3輸出緩衝級設計 110
5.3.1第三諧波失真項(Third harmonic distortion, HD3) 112
5.3時脈緩衝器設計 112
5.4整體電路模擬 114
5.5電路實作與量測 121
5.6總結 128
第6章 結論 130
參考文獻 131
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[39] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari and J. Godin, "A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology," 2012 20th Telecommunications Forum (TELFOR), Belgrade, 2012, pp. 502-505.
[40] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13 μm CMOS Switched Cascode Track-and-Hold Amplifier,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 7, pp. 512-516, Jul., 2010.
指導教授 張鴻埜(Hung-Yeh Chang) 審核日期 2018-7-19
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