博碩士論文 104521119 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:8 、訪客IP:54.161.100.24
姓名 廖紫涵(Tzu-Han Liao)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 支援IEEE.802.11ad 雙碼率之低密度奇偶檢查編碼器及解碼器的設計與實作
(Design and Implementation of IEEE 802.11ad LDPC Encoder and Decoder for Two Code-Rates)
相關論文
★ 具輸出級誤差消除機制之三位階三角積分D類放大器設計★ 應用於無線感測網路之多模式低複雜度收發機設計
★ 用於數位D類放大器的高效能三角積分調變器設計★ 交換電容式三角積分D類放大器電路設計
★ 適用於平行處理及排程技術的無衝突定址法演算法之快速傅立葉轉換處理器設計★ 適用於IEEE 802.11n之4×4多輸入多輸出偵測器設計
★ 應用於無線通訊系統之同質性可組態記憶體式快速傅立葉處理器★ 3GPP LTE正交分頻多工存取下行傳輸之接收端細胞搜尋與同步的設計與實現
★ 應用於3GPP-LTE下行多天線接收系統高速行駛下之通道追蹤與等化★ 適用於正交分頻多工系統多輸入多輸出訊號偵測之高吞吐量QR分解設計
★ 應用於室內極高速傳輸無線傳輸系統之 設計與評估★ 適用於3GPP LTE-A之渦輪解碼器硬體設計與實作
★ 下世代數位家庭之千兆級無線通訊系統★ 協作式通訊於超寬頻通訊系統之設計
★ 適用於3GPP-LTE系統高行車速率基頻接收機之設計★ 多使用者多輸入輸出前編碼演算法及關鍵組件設計
檔案 [Endnote RIS 格式]    [Bibtex 格式]    至系統瀏覽論文 (2023-8-20以後開放)
摘要(中) 由於IEEE.802.11ad 標準需求高達7 Gbps的數據吞吐速度,也使用較高頻的頻段,造成資料傳輸過程中會有許多通道與雜訊效應影響效能,因此錯誤更正碼的是系統中不可或缺的存在。近年來透過積體技術的蓬勃發展,使得高複雜度的低密度奇偶檢查碼之編碼與解碼方式有了實現的可能,低密度奇偶檢查碼擁有描述簡單並能平行處理的優點,很適合以硬體實現來達成高吞吐率的需求。本文選用支援IEEE 802.11ad 之1/2與3/4兩種碼率的低密度奇偶檢查碼來設計與實作其編解碼器,在編碼器方面運用類循環(QC)-LDPC碼的特性並搭配位移累加暫存器 (Shift Register Adder Accumulator, SRAA)為主體設計出可重配置硬體架構,使用312.5MHz的時脈,可達10Gbps的吞吐率。為了降低複雜度,我們採用了具有疊代性的置信傳播(Belief Propagation)的解碼演算法-最小值總和演算法(Min-Sum Algorithm),並以行層排程(Column-Based Layer Scheduling)來降低所需的解碼遞迴次數。4大列的行層排程可降低現存洪水式(flooding)的解碼器繞線量巨大的問題,每個時脈周期可更新四分之一的變數節點與所有的檢查節點,四個時脈周期可以完成所有的變數節點更新,內部資料流採用6位元的格式,並發揮行層排程的優勢來節省記憶體的使用量。
摘要(英) IEEE 802.11ad standard supports data rate up to 7Gbps under the 60GHz frequency band. Thus, error correction code is an indispensable component for this communication system. Due to the rapid development of IC technology during these decades, realization of low density parity check code becomes no more intractable. The encoding and decoding of the low-density parity-check code can be processed in parallel, and thus it is very suitable for hardware implementation to accelerate the throughput. In this thesis, design and implementation of an LDPC encoder and decoder that support 0.5 and 0.75 code rates for IEEE 802.11ad are presented. For the encoder design, the properties of QC-LDPC code are exploited and the shift register adder accumulator (SRAA) is employed as the basic functional block. At 312.5 MHz clock frequency, it achieves throughput of 10Gbps. For the decoder design, in order to reduce the complexity, we use the iterative min-sum algorithm derived from the concept of belief propagation as our decoding algorithm and the column-based layer scheduling is also adopted. It takes 4 clock cycles to complete the soft information update of all variable nodes. The column-based scheduling can reduce the huge wire cost of decoders with flooding-based scheduling. Six-bit wordlength is used for internal computation. We also exploit the advantage of the column-based scheduling to save the memory requirements.
關鍵字(中) ★ 低密度奇偶檢查碼
★ 解碼器
★ 錯誤更正碼
★ 最小值總和演算法
★ 總和乘積演算法
★ 編碼器
關鍵字(英) ★ Low density parity check code
★ Decoder
★ Error correct code
★ Min sum algorithm
★ Sum product algorithm
★ Encoder
論文目次 摘要 i
Abstract ii
目錄 iii
圖表目錄 v
第一章 緒論 1
1.1 研究動機 1
1.2 研究方法 2
1.3 論文組織 3
第二章 低密度奇偶檢查碼 4
2. 1低密度奇偶檢查碼(Low Density Parity Check)介紹 4
2. 2 IEEE 802.11ad介紹 7
2.2. 1 IEEE 802.11ad標準下各參數特性 7
2.2. 2 802.11ad 標準之物理層 10
2. 3 802.11ad下之低密度奇偶檢查碼 10
第三章 LDPC之編碼器介紹 13
3. 1規則及不規則形式的LDPC介紹 13
3. 2 QC-LDPC的介紹及其使用原因 14
3. 3根據有限幾何(Finite Geometries)來構造LDPC碼 15
3. 4 QC-LDPC的線性編碼 16
3. 5 編碼器硬體設計 21
3. 6 Encoder 前端設計 25
3.6. 1 單載波封包前導碼(SC packet preamble) 26
3.6. 2 頭碼設計 26
3.6. 3 擾亂器 28
3.6. 4 編碼器 I/O interface 34
3. 7 編碼器硬體模擬結果 35
第四章 LDPC之解碼器介紹 41
4. 1 解碼器使用之演算法 41
4.1.2總和乘積演算法(Sum-Product Algorithm) 42
4.1.3最小值總和演算法(Min-Sum Algorithm) 46
4.1.4搭配行層排程之最小值總和演算法 49
4. 2 編碼器之硬體架構設計 55
第五章 結論 67
參考文獻 68
參考文獻 [1] R. Gallager, “Low-Density Parity-Check Codes,” IRE Trans. Inf. Theory, vol. 7, pp. 21–28, Jan. 1962.

[2] M. Mansour and N. Shanbhag , “High-throughput LDPC decoders,” IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 976–996, Dec. 2003.

[3] J. Zhang and M. Fossorier, “Shuffled iterative decoding,” IEEE Transactions on Communications, vol. 53, no. 2, pp. 209–213, Feb. 2005.

[4] M. P. C. Fossorier, M. Mihaljevic, and H. Imai, “Reduced Complexity Iterative Decoding of Low-density Parity Check Codes Based on Belief Propagation, ” IEEE Trans. Communications., vol. 47, no. 5, pp. 673–680, May, 1999.

[5]J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X. Y. Hu, “Reduced-complexity Decoding of LDPC Codes,” IEEE Trans. Communications, vol. 53, no. 8, p.1288–1299, Aug. 2005.

[6] Richardson and Rudiger L., Thomas J, “Efficient Encoding of Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 47, no.2, P638-656, Feb 2001

[7] Chih-Hsien Lin, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, and Shyh-Jye Jou, “Parallel Scrambler for High-Speed Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 53,Issue 7, p.558-562, July 2006

[8] Xiao-Yu Hu, E.Eleftheriou, D.M. Arnold, “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” IEEE Global Telecommunications Conference (Cat. No.01CH37270), 25-29 Nov. 2001, p.1036~1036E

[9] H. Motozuka, N. Yosoku, T. Sakamoto, T. Tsukizawa, N. Shirakata and K. Takinami, "A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS,"2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP), Orlando, FL, 2015, pp. 1289-1292.

[10] P. Schlafer et al., "Error resilience and energy efficiency: An LDPC decoder design study,"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp. 588-593.

[11] Y. S. Park, D. Blaauw, D. Sylvester and Z. Zhang, "Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM," in IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 783-794, March 2014.

[12] M. Weiner, M. Blagojevic, S. Skotnikov, A. Burg, P. Flatresse and B. Nikolic, "27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI,"2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 464-465.

[13] ISO/IEC/IEEE International Standard for Information technology--Telecommunications and information exchange between systems--Local and metropolitan area networks--Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 3: Enhancements for Very High Throughput in the 60 GHz Band (adoption of IEEE Std 802.11ad-2012).

[14] Hung, Shiang-Yu, " Design and Implementation of Multiple Code-rates LDPC Decoder and Encoder for IEEE 802.15.3c", Master thesis, National Chiao Tung University, Sep 2010.
指導教授 蔡佩芸(Pei-Yun Tsai) 審核日期 2018-8-23
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明