高頻元件重佈線層銅電鍍製程與光阻裂紋研究

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邱奕桓(Yi-Huan Chiu) 查詢紙本館藏

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機械工程學系在職專班

論文名稱

高頻元件重佈線層銅電鍍製程與光阻裂紋研究
(A redistribution layer study of photoresist crack and copper plating for high frequency device)

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摘要(中)

RDL(Re-distribution layer)製程應用在高頻元件可包含銅線路及凸塊，此時應用甲基磺酸電鍍(methanesulfonic acid ,MSA)，由於銅離子濃度可以提高，電流密度也高，此方法與傳統的硫酸銅電鍍線路比較可節省生產成本，但此應用於重佈線層光阻在密集線路區域，經銅電鍍製程後，易發生光阻破裂的問題。
此光阻破裂問題必需要完全避免，因此，為了避免線路短路及降低二次電鍍的風險，以增加製程穩定性，本研究利用實驗的方式，改變不同的製程條件，逐步釐清造成光阻破裂的非影響因素，如軟烤溫度、軟烤時間、曝光量、曝光間距、光源種類、線路圖形、電鍍添加劑、電鍍沉積速度等，以及影響因素，包含光阻厚度、電鍍銅厚度、光阻尺寸等，如此，找到可影響此缺陷數量的關鍵因素，根據實驗的結果，發現可依此訂定製程設計規則表，例如銅厚度在12μm時，光阻寬度大於等於10μm以上，即線距大於等於10μm以上，則不會發生此光阻破裂的問題，使重佈線層的光阻保持完整，進而降低銅滲鍍及短路的風險。結果顯示，此光阻裂紋缺陷會藉由製程條件的搭配，此缺陷明顯獲得改善。

摘要(英)

The re-distribution layer (RDL) application in high frequency component can include copper lines and bumps, the application of methanesulfonic acid (MSA) plating at this time, due to the copper solution’s ion concentration can be increased and high current density. This method compared with the traditional copper sulfate plating could save more costs, but the dense line of photo-resist under this application is easily crack after plating procedure. Therefore, in order to avoid short circuit and reduce the risk of secondary plating, and then increase the stability of the process, this study used experimental methods to test the different process conditions, and gradually to clarify the cause of the non-influencing factors of photoresist crack such as soft roasting temperature, soft roasting time, exposure, exposure spacing, light source type, circuit pattern, plating additive, plating deposition rate, etc., and influencing factors including photoresist thickness, copper plating thickness, photoresist size .After those study, we could got the key factors that can affect the number of defects. According to the experimental results, the design guidelines is summarized. Such as copper thickness 12μm, the photoresist width greater than or equal to 10 or more. That spacing is greater than and Equal to 10 or more. The cracking of the photo-resist does not occur after plating. The photoresist of the re-distribution layer keeps complete to next stage, and the risk of copper plating and short were reduced. The results show that this photoresist crack defects will be matched by the process conditions, this defect has been significantly improved.

關鍵字(中)

★ 光阻裂紋
★ 甲基磺酸電鍍
★ 重佈線層

關鍵字(英)

★ photoresist crack
★ Methanesulfonic Acid plating
★ Re-distribution layer (RDL)

論文目次

中文摘要 ………………………………………………………………………………………… i
英文摘要 ……………………………………………………………………………………………… ii
誌謝 ……………………………………………………………………………………………………… iii
目錄 ……………………………………………………………………………………………………… iv
圖目錄 ………………………………………………………………………………………………… viii
表目錄…………………………………………………………………………………………………… xii
一、緒論………………………………………………………………………………………………… 1
1-1前言…………………………………………………………………………………………………………1
1-1-1 重佈線製程應用………………………………………………………………………1
1-1-2 導電層沉積………………………………………………………………………………1
1-1-3 光阻塗佈……………………………………………………………………………………2
1-1-4 曝光……………………………………………………………………………………………2
1-1-5 光阻顯影……………………………………………………………………………………2
1-1-6 表面處理……………………………………………………………………………………2
1-1-7 銅電鍍…………………………………………………………………………………………2
1-1-8 光阻去除……………………………………………………………………………………3
1-1-9 導電層蝕刻…………………………………………………………………………… 3
1-2研究動機與目的 …………………………………………………………………………… 4
1-3論文架構 ……………………………………………………………………………………… 11
二、文獻整理與基本回顧 …………………………………………………………………… 12
2-1晶圓級晶片尺寸封裝(WLCSP) ………………………………………………… 12
2-1-1 WLCSP與一般封裝的差異 ……………………………………………………12
2-1-2 RDL封裝技術 ………………………………………………………………………… 13
2-2重佈線製程介紹 …………………………………………………………………………… 14
2-2-1光阻介紹 …………………………………………………………………………………… 14
2-2-2塗佈製程 …………………………………………………………………………………… 16
2-2-3曝光製程 …………………………………………………………………………………… 17
2-3光阻的不同破裂方式 ………………………………………………………………… 18
2-4熱應力對於TSV結構影響…………………………………………………………… 18
2-5熱應力理論模型分析 ………………………………………………………………… 20
2-6軟烤溫度對光阻開孔的影響 …………………………………………………… 22
2-7 銅電鍍液使用於重佈線層與凸塊製程…………………………………… 22
2-8 高頻被動元件之設計………………………………………………………………… 22
三、實驗方法與設備…………………………………………………………………………… 23
3-1實驗流程………………………………………………………………………………………… 23
3-2實驗步驟………………………………………………………………………………………… 27
3-3實驗設備………………………………………………………………………………………… 28
四、結果與討論…………………………………………………………………………………… 32
4-1電鍍銅厚的變化對裂紋影響…………………………………………………… 32
4-2塗佈製程的軟烤溫度與時間對裂紋的影響………………………… 36
4-3分段軟烤對電鍍後光阻裂紋的影響……………………………………… 38
4-4接觸與非接觸軟烤對光阻裂紋的影響………………………………… 39
4-5不同的光阻厚度對光阻裂紋的影響……………………………………… 39
4-6不同光阻系統對光阻裂紋的影響. ……………………………………… 45
4-7不同曝光能量對光阻裂紋的影響…………………………………………… 47
4-8不同曝光間距對於光阻裂紋的影響……………………………………… 50
4-9不同轉角設計對光阻裂紋的影響…………………………………………… 53
4-10不同線路尺寸與光阻裂紋的關係………………………………………… 54
4-11不同曝光源對光阻裂紋的影響……………………………………………… 56
4-12電鍍前無表面處理對光阻裂紋的影響………………………………… 59
4-13不同電鍍沉積速度對光阻裂紋的影響………………………………… 60
4-14分解電鍍流程中，釐清各步驟對光阻裂紋的影響…………… 62
4-15不同電鍍液溫度對光阻裂紋的影響……………………………………… 63
4-16不同添加劑比例對光阻裂紋的影響……………………………………… 64
4-17逐步增加銅厚對於光阻裂紋的影響……………………………………… 65
4-18電鍍液種類對光阻裂紋的影響……………………………………………… 67
4-19小結(製程條件與光阻裂紋之關聯性) ……………………………… 68
五、結論 ………………………………………………………………………………………… 70
參考文獻 …………………………………………………………………………………………… 72

參考文獻

[1]蕭獻賦，實用IC封裝，初版，五南圖書出版，台北市，民國104年。
[2]王家鴻，「Solder Bump製程應用在Wafer Level CSP RDL結構可靠度提升 Study」，國立交通大學，碩士論文，民國九十九年。
[3]莊達人，VLSI製造技術，四版五刷，高立圖書出版，台北市，民國89年。
[4]蔡文勇，「I-line光阻劑於TFT LCD Array製程之應用及評估」，國立中央大學，碩士論文，民國九十五年。
[5]TOKYO OHKA KOGYO CO., LTD., Chemistry of Novolak-DNQ Based Resists,(1994)。
[6]李玥瑩，「不同破裂方式於光阻薄膜引發破裂波紋受加馬射線影響之探討」，國立清華大學，碩士論文，民國一○一年。
[7] C.-T. Ko and K.-N. Chen, “Wafer-level bonding/stacking technology
for 3D integration,” Microelectron. Rel., vol. 50, no. 4, pp. 481–488,
Apr. 2010.
[8] J. U. Knickerbocker et al., “Three-dimensional silicon integration,” IBM
J. Res. Develop., vol. 52, no. 6, pp. 553–569, Nov. 2008.
[9] T. S. Cale, J.-Q. Lu, and R. J. Gutmann, “Three-dimensional integration
in microelectronics: Motivation, processing, and thermomechanical
modeling,” Chem. Eng. Commun., vol. 195, no. 8, pp. 847–888, 2008.
[10] J. H. Lau, “Overview and outlook of through-silicon via (TSV) and 3D
integrations,” Microelectron. Int., vol. 28, no. 2, pp. 8–22, 2011.
[11] P. Ramm, A. Klumpp, J. Weber, and M. M. V. Taklo, “3D system-onchip
technologies for more than Moore systems,” Microsyst. Technol.,
vol. 16, no. 7, pp. 1051–1055, 2010.
[12] J.-Q. Lu, “3-D hyperintegration and packaging technologies for micronano
systems,” Proc. IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
[13] Z. Wang, “3-D integration and through-silicon vias in MEMS and
microsensors,” J. Microelectromech. Syst., vol. 24, no. 5, pp. 1211–1244,
Oct. 2015.
[14] X. Zhang et al., “Heterogeneous 2.5D integration on through silicon
interposer,” Appl. Phys. Rev., vol. 2, no. 2, p. 021308, 2015.
[15] Y. Ding, Y. Yan, Q. Chen, S. Wang, R. Su, and H. Dang, “Analytical
solution on interfacial reliability of 3-D through-silicon-via (TSV)
containing dielectric liner,” Microelectron. Rel., vol. 54, nos. 6–7,pp. 1384–1391, 2014.
[16] E. J. Cheng and Y.-L. Shen, “Thermal expansion behavior of throughsilicon-via structures in three-dimensional microelectronic packaging,”
Microelectron. Rel., vol. 52, no. 3, pp. 534–540, Mar. 2012.
[17] Y. S. Chan and X. Zhang, “Clarification of stress field measured by
multiwavelength micro-Raman spectroscopy in the surrounding silicon
of copper-filled through-silicon vias,” IEEE Trans. Compon., Packag.,
Manuf. Technol., vol. 4, no. 6, pp. 1010–1014, Jun. 2014.
[18] Q. Ma, K. Wu, and Z. Wang,“Thermal stresses of TSVs with silicon post conductors and polymer insulators.” IEEE Trans. Compon., Packag.,Manuf. Technol., vol. 6, no. 12, pp. 1847–1854, Dec. 2016.
[19] S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P. S. Ho, R. Huang, "Impact of near-surface thermal stresses on interfacial reliability of through-silicon-vias for 3-D interconnects", IEEE Trans. Device Mat. Reliab., vol. 11, no. 1, pp. 35-43, Mar. 2011.
[20]卓慶華，「光阻烘烤製程的不均勻性對CD之影響」，國立交通大學，碩士論文，民國九十九年
[21]夏峪霖，「利用光皆子光阻流變特性的控制以縮短彩色濾光片固烤製程週期」，國立交通大學，碩士論文，民國九十八年。
[22]S. Chung, E. Kuo, and M. Tseng,”Bump Shape Control on High Speed Copper Pillar Plating Process in Lead-Free Wafer Level Packaging”, Microsystems, Packaging, Assembly and Circuits Technology Conference, page 432-435,Taipei,Taiwan,21-23 Oct. 2009
[22]洪瑞原，「高頻被動元件之研究與製作」私立中原大學，碩士論文，民國九十一年。
[24]http://semiust.blogspot.tw/2012/12/tel-clean-track-act8-12-mark-78.html 2018/1/11 11:49PM
[25]https://www.suss.com/en/products-solutions/mask-aligner/ma-ba-6 2018/1/13 15:33 PM
[26] http://www.jkuv.cn/newsshow-17-407.html 2018/2/1 00:10
[27]http://www.giantguang.com.tw/prodDetail.asp?id=129]

指導教授

傅尹坤

審核日期

2018-7-4

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