利用線穿隧及非均勻通道厚度提升三五族 穿隧場效電晶體性能之研究

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王秋婷(Chiu-Ting Wang) 查詢紙本館藏

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電機工程學系

論文名稱

利用線穿隧及非均勻通道厚度提升三五族穿隧場效電晶體性能之研究
(Performance Enhancement of III-V Tunnel FETs considering Line Tunneling and Non-uniform　Channel Thickness)

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摘要(中)

隨著CMOS尺寸微縮，降低供應電壓，以降低功率消耗，是現階段CMOS積體電路最大的目標，低功率消耗之應用包含IoT (Internet-of-Things) 技術以及穿戴式電子用品等。傳統金氧半場效電晶體(MOSFET)在室溫下受到波茲曼分布的限制，其次臨界擺幅(Subthreshold swing)無法低於60mV/dec。因此，具有較陡峭次臨界擺幅之穿隧場效電晶體(Tunnel FETs, TFETs)，隨之被提出，因其次臨界擺幅表現可低於60mV/dec，在降低供應電壓的條件下(低於0.5伏特)，其效能表現可優於傳統金氧半場效電晶體的效能，是半導體積體電路應用在未來發展最為重要的關鍵。三五族異質接面穿隧場效電晶體因其較低的能隙(Band-gap)，可增加穿隧機率，更有利於製作為穿隧場效電晶體以提升其導通電流。三五族材料因為其較低的能態密度，使得三五族穿隧場效電晶體在高操作電壓時，不易得到高導通電流，但在低操作電壓時，其導通電流仍可表現優於傳統金氧半場效電晶體。因此本論文建立三五族(GaAsSb/InGaAs)穿隧場效電晶體TCAD模型，探討三五族穿隧場效電晶體之結構優化，分析並提出可提升導通電流之最佳結構。
　　第一部分為利用增加磊晶層(Epitaxial layer)在閘極(Gate)及源極(Source)間產生線穿隧(Line tunneling)接面電流，增加穿隧面積進而提升導通電流，並加以探討不同通道厚度(Tch)、同質接面(Homo-junction)材料與異質接面(Hetero-junction)材料的穿隧能障(Effective tunneling barrier heigh, Ebeff)、磊晶層厚度(Tepi)、閘極與源極間交疊長度(Lovs)以及閘極與汲極(Drain)間非交疊長度(Underlap length, Lund)對線穿隧場效電晶體電性之影響，並提出最佳化線穿隧場效電晶體之設計。與一般超薄層點穿隧場效電晶體(UTB p-i-n TFET w/o Tepi)之電特性做比較，Lovs為10nm以及Tepi為2nm的線穿隧場效電晶體，導通電流能有3.3倍的提升，Ion並能達到406 (μA/μm) @ Vdd = 0.5V。
　　第二部分為利用非圴勻通道厚度，使局部較窄的通道其能隙受量子侷限效應的影響而增加，優化非均勻通道厚度(Non-uniform Tch)，達到同時改善截止電流(Ioff)以及導通電流，首先探討不同源極摻雜濃度(Ns)、汲極摻雜濃度(Nd)以及通道厚度(Tch)對異質接面第二型(Type II)以及第三型(Type III)均勻通道厚度(Uniform Tch)穿隧場效電晶體電性之影響，並更進一步探討元件結構改變對非均勻通道厚度穿隧場效電晶體性能之影響，例如：源極與通道間厚度(Ts)、汲極與通道間厚度(Td)以及較厚通道端長度(Lw)，最後一部分利用汲極與閘極間非交疊(Lund)設計進一步改善Type III截止電流，當Lund = 8nm時，截止電流可以有70.5%的改善。

摘要(英)

Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (Vdd) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as supply voltage scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperature. Tunneling field-effect transistors (TFETs) have been actively explored to tackle this problem and provide steep subthreshold slope below 60mV/dec [1].

Tunnel field-effect transistors (Tunnel FETs, TFETs), which have a subthreshold swing below 60 mV/decade, were proposed as an alternative to conventional MOSFETs in response to the quest for lower power consumption integrated circuits. III-V channel materials become promising materials for TFETs due to their lower bandgap which leads to better tunneling efficiency. However, III-V TFETs still show lower drive current than conventional Si MOSFET at high supply voltage due to their low density of states.

This work aims at structure optimization of III-V TFETs for improving the drive current based on InGaAs/GaAsSb heterostructures. The InGaAs/GaAsSb TFET simulation framework with TCAD tool was established in this work. First, a novel TFET structure with line tunneling was proposed and analyzed comprehensively. By inserting an expitaxial layer between source and gate dielectric regions, TFET consists both lateral point tunneling and line tunneling. Compared with the conventional p-i-n TFET with point tunneling only. The on current of TFETs with epi layer and line tunneling can be further increased due to the increased tunneling area. We analyze the impact of device design on the TFET with epi layer comprehensively. The impacts of epi layer thickness (Tepi), gate-to-source overlap length (Lovs), source thickness, and gate-to-drain underlap length (Lund) on the Id-Vg characteristics of heterojunction III-V TFETs were analyzed comprehensively in this work. This study provides the device design guidelines for performance enhancement of TFETs with epi layer. Compared with the conventional TFET without epitaxial layer, the heterojunction TFET with epitaxial layer and gate to source overlap length = 10 nm shows 3.3 times higher on currents and Ion = 406 (μA/μm) at Vdd = 0.5V.

Sencond, GaAs1-xSbx/In1-yGayAs heterojunction TFETs with bandgap engineering by using non-uniform channel thickness (Tch) are analyzed comprehensively for improving Ion and suppressing ambipolar leakage. Quantum confinement induced bandgap widening as a function of Tch is considered. We analyze the impact of source doping concentration (Ns), drain doping comcentration (Nd), and channel thickness (Tch) on the Id-Vg characteristics of uniform Tch Type II and Type III heterojunction TFETs. The impact of source/channel junction thickness (Ts), drain/channel junction thickness (Td), and thicker channel length (LW) on the Id-Vg characteristics of non-uniform type-II TFETs are also analyzed comprehensively. Finally, the Ioff of type-III non-uniform TFETs can be further reduced by using gate-to-drain underlap design. The Ioff can be improved by 70% as Lund changes from 0 nm to 8 nm.

關鍵字(中)

★ 穿隧場效電晶體
★ 磊晶層
★ 線穿隧
★ 點穿隧
★ 同質接面
★ 異質接面

關鍵字(英)

★ Tunnel FET (TFET)
★ epitaxial layer
★ line tunneling
★ point tunneling
★ homo-junction
★ hetero-junction

論文目次

摘要 I
Abstract III
致謝 V
目錄 VII
圖目錄 X
表目錄 XVIII
第一章導論 1
1.1 背景與相關研究 1
1.2 研究動機 12
1.3 論文架構 13
第二章線穿隧場效電晶體之結構優化及性能提升研究 14
2.1 前言 14
2.2 線穿隧場效電晶體之元件設計 16
2.2.1 元件模擬參數與元件結構 16
2.2.2 分析有效能障(Effective Barrier)對線穿隧場效電晶體之影響 20
2.2.3 分析磊晶層厚度(Epitaxial layer thickness)對線穿隧場效電晶體之影響 23
2.2.4 分析閘極與源極間交疊長度對線穿隧場效電晶體之影響 27
2.2.5分析閘極與汲極間非交疊長度以及源極厚度對線穿隧場效電晶體之影響 30
2.3 線穿隧場效電晶體加入反摻雜(Counter doping)之研究 34
2.3.1 元件模擬參數與元件結構 34
2.3.2 分析反摻雜在異質接面穿隧式場效應電晶體之影響 36
2.4 線穿隧場效電晶體考慮不同銻砷化鎵/砷化銦鎵比例之研究 40
2.4.1 元件模擬參數與元件結構 40
2.4.2 分析有效能障對垂直線穿隧之影響 42
2.4.3 分析閘極及源極間交疊長度之影響 46
2.5 結論 50
第三章非均勻通道厚度(Non-uniform Channel Thickness)對穿隧場效電晶體性能之研究 53
3.1 前言 53
3.2 元件模擬參數與元件結構 54
3.3 均勻通道厚度穿隧場效電晶體之電性分析 57
3.3.1 分析量子侷限效應之影響 57
3.3.2 分析源極及汲極摻雜濃度之影響 58
3.4 非均勻通道厚度穿隧場效電晶體之電性分析 61
3.4.1 元件設計之最佳化 61
3.4.2 分析閘極與汲極非交疊長度對異質接面第三型穿隧場效電晶體之影響 67
3.5 結論 71
第四章總結 73
參考文獻 76
附錄 80
5.1 線穿隧場效電晶體之元件設計 80
5.1.1分析有效能障(Effective Barrier)對線穿隧場效電晶體之影響 80
5.1.2 分析磊晶層厚度(Epitaxial layer thickness)對線穿隧場效電晶體之影響 82
5.1.3分析閘極與源極間交疊長度對線穿隧場效電晶體之影響 86
5.1.4分析反摻雜在同質接面穿隧式場效應電晶體之影響 91

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指導教授

胡璧合(Vita Pi-Ho Hu)

審核日期

2018-7-24

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