參考文獻 |
[1] 洪政亮, “高速有線傳輸系統之時脈產生器關鍵技術,” 博士論文, 國立中央大學, 2014.
[2] VESA DisplayPort Standard Revision 1.2, VESA, Jan 2010.
[3] Serial ATA International Organization: Serial ATA Revision 3.1, SATA-IO, 2011
[4] Universal Serial Bus 3.2 Specification Revision 1.0, USB-IO, 2013
[5] PCI Express® Base Specification Revision 3.0, PCI-SIG, 2010
[6] Y. -H. Kao, and Y. –B. Hsieh, “A fully integrated spread-spectrum clock generator using a dual-path loop filter,” in Proc. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006, pp. 7–10.
[7] Y. -B. Hsieh, and Y. -H. Kao, “A new spread-spectrum clock generator for SATA using double modulation schemes,” in Proc. IEEE Custom Integrated Circuits Conference, Sept. 2007, pp. 297–300.
[8] Y. -B. Hsieh, and Y. -H. Kao, “A fully integrated spread-spectrum clock generator by using direct VCO modulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1845–1853, Aug. 2008.
[9] C. -Y. Yang, C. -H. Chang, and W. -G. Wong, “A 3.2-GHz down-spread spectrum clock generator using a nested fractional topology,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. 91, no. 2, pp. 497–503, Feb. 2008.
[10] C. -Y. Yang, C. -H. Chang, and W. -G. Wong, “A Δ-Σ PLL-based spread spectrum clock generator with a ditherless fractional topology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 51–59, Jan. 2009.
[11] K. -H. Cheng, C. -L. Hung, and C. -H. Chang, “A 0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phase-rotating technique,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1198–1213, May. 2011.
[12] H. Lee, O. Kim, G. Ahn, and D. Jeong, "A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18um CMOS," IEEE Int. Solid-State Circuits Conference, 2005, pp. 162–163.
[13] F. Pareschi, G. Setti, and R. Rovatti, “A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2577–2587, Oct. 2010.
[14] S. -G. Bae, G. Kim, and C. Kim, “A 5-GHz sub-sampling PLL based spread-spectrum clock generator by calibrating the frequency deviation” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp.1132–1136, Oct. 2017.
[15] K. -B. Hardin, J. -T. Fessler, and D. -R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Symposium on Electromagnetic Compatibility, 1994, pp. 227–231.
[16] C. -Y. Lin, T. -J. Wang, and T. -H. Lin, “A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2017. pp. 1198–1213.
[17] H. -H. Chang, I. -H. Hua, and S. -I. Liu, "A spread-spectrum clock generator with triangular modulation," IEEE J. Solid-State Circuits, vol.38, no.4, pp. 673–676, Apr. 2003.
[18] C. -H. Wong, and T. -C. Lee, “A 6-GHz self-oscillating spread-spectrum clock generator,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no.5, pp. 1264–1273, May 2013.
[19] K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang, and J. -W. Miaw, “A spread-spectrum clock generator using fractional-N PLL controlled delta-sigma modulator for Serial-ATA III,” in Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr. 2008, pp. 1–4.
[20] T. Kawamoto, M. Suzuki, and T. Noto, “1.9-ps jitter, 10.0-dBm-EMI reduction spread-spectrum clock generator with autocalibration VCO technique for Serial-ATA application,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1118–1126, May. 2014.
[21] D. -D. Caro, F. Tessitore, G. Vai, N. Imperato, N. Petra, E. Napoli, C. Parrella, and A. -G. -M. Strollo, “A 3.3 GHz spread-spectrum clock generator supporting discontinuous frequency modulations in 28 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2074–2089, Sept. 2015.
[22] S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim, and D. -K. Jeong, “An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation,” in Symposium on VLSI Circuits, Jun. 2015, pp. C136–C137.
[23] I. -T. Lee, S. -H. Ku, and S. -I. Liu, “An all-digital spread-spectrum clock generator with self-calibrated bandwidth,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 10, pp. 2813–2822, Nov. 2013.
[24] D. sheng, C. -C. Chung, and C. -Y. Lee, “A low-power and portable spread spectrum clock generator for SoC applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113–1117, Jun. 2011.
[25] S. -Y. Lin, and S. -I. Liu, “A 1.5 GHz all-digital spread spectrum clock generator,” IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009.
[26] D. -D. Caro, C. -A. Romani, N. Petra, A. -G. -M. Strollo, and C. Parrella, “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048–1060, Mar. 2010.
[27] S. Damphousse, K. Ouici, A. Rizki, and M. Mallinson, “All digital spread spectrum clock generator for EMI reduction,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 145–150, Jan. 2007.
[28] N. -D. Dalt, P. Pridnig, and W. Grollitsch, “An all-digital PLL using random modulation for SSC generation in 65nm CMOS,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2013, pp. 252–253.
[29] C. -C. Chung, D. Sheng, and W. -D. Ho, “A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,” in Proc. VLSI Design, Automation and Test (VLSI-DAT), April. 2012, pp. 1–4.
[30] C. -C. Chung, D. Sheng, and W. -D. Ho, “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983–987, May 2015.
[31] T. Sudo, H. Sasaki, N. Masuda, and J. -L. Drewniak, “Electromagnetic interference (EMI) of system-on-package (SOP),” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 304–314, May 2004.
[32] 花怡慧, “66/133/266MHz展頻時脈產生器之設計與製作,” 碩士論文, 國立台灣大學, 2002.
[33] A. Shoval, W. -M. Snelgrove, and D. -A. Johns, “A 100 Mb/s BiCMOS adaptive pulse-shaping filter,” IEEE Journal on Selected Areas in Communications, vol. 13, pp. 1692–1702, Dec. 1995.
[34] J. Kim, D. -G. Kam, P. -J. Jun, and J. Kim, “Spread spectrum clock generator with delay cell array to reduce the electromagnetic interference,” IEEE Transactions on Electromagnetic Compatibility, vol. 47, no. 4, pp. 908–920, Nov. 2005.
[35] 黃映祥, “具高速相位選擇器之六十億赫茲全數位展頻時脈產生器,” 碩士論文, 國立中央大學, 2013.
[36] V. Kratyuk, P. -K. Hanumolu, U. -K. Moon, and K. Mayaram, “A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007.
[37] C. -M. Hsu, M. -Z. Straayer, M. -H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2776–2786, Dec. 2008.
[38] D. -H. Oh, D. -S. Kim, S. Kim, D. -K. Jeong, and W. Kim, “A 2.8Gb/s all-digital CDR with a 10b monotonic DCO,” in Proc. IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Feb. 2007, pp. 222–598.
[39] D. -S. Kim, H. Song, T. Kim, S. Kim, and D. -K. Jeong, “A 0.3–1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2300–2311, Nov. 2010.
[40] H. Song, D. -S. Kim, D. -H. Oh, S. Kim, and D. -K. Jeong, “A 1.0–4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 424–434, Feb. 2011.
[41] B. -W. Garlepp, K. -S. Donnelly, J. Kim, P. -S. Chau, J. -L. Zerbe, C. Huang, C. -V. Tran, C. -L. Portmann, D. Stark, Y. -F. Chan, T. -H. Lee, and M. -A. Horowitz, “A portable digital DLL for high-speed CMOS interface circuits,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 632–644, May 1999.
|