博碩士論文 105521039 詳細資訊




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姓名 楊育銜(Yu-Sian Yang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於SATA III之 6 GHz 展頻時脈迴路
(A 6 GHz SATA-III Spread Spectrum Clock Generator)
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檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 (2024-7-31以後開放)
摘要(中) 本論文提出了以次取樣鎖相迴路為架構的6 GHz展頻時脈電路設計,符合SATA III之展頻時脈規格,使用三角波向下展頻;架構上,在次取樣鎖相迴路中,由於缺少除頻器而具有較大迴路頻寬,因此擁有較佳的抖動量;在次取樣檢測器中,以壓控振盪器取樣輸入參考訊號,替換原本外接輸入參考訊號,與次取樣檢測器另一組輸入端點,壓控振盪器差動輸出,皆為同源訊號而失鎖往固定方向,利用此狀態來對時脈展頻,並使用適應器偵測三角波波峰與波谷的頻率,適時調整追鎖方向,來實現平滑三角波展頻電路,因此電路同時具有較大迴路頻寬與簡易架構兩大優勢,而具有較小核心面積、功耗和較大的電磁干擾抑制量與較佳的抖動量;另外,為了減少類比濾波器面積大小,本論文使用電流式電容放大技術來大量縮減面積。

本論文電路使用TSMC 40 nm 1P9M (TN40G) CMOS 製程來實現,電路操作電壓為0.9 V,輸入參考訊號頻率為100 MHz,輸出時脈訊號頻率為6 GHz。次取樣鎖相迴路的展頻時脈產生器的部份則是使用三角波調變式的展頻可以得到21 dB的電磁干擾抑制量。電路所占面積為0.13 mm2,晶片所佔面積為1.11 mm2。
摘要(英) A 6 GHz SATA-III spread-spectrum clock generator in sub-sampling loop structure is presented in this thesis. It uses triangular spread wave and down-spread technique. In structure, the loop without divider has wider loop bandwidth compared with phase-locked loop, so it has better jitter performance. In spread-spectrum clock, we replaced external reference signal of sub-sampled phase detector with that signal triggered by voltage-controlled oscillator. The design makes input signals of sub-sampled phase detector, including the signal triggered by voltage-controlled oscillator and differential output of voltage-controlled oscillator, come from voltage-controlled oscillator and lose lock in inherent direction. Therefore, if we carefully adjust the direction and monitor turning points, we can perform smooth triangular wave spread spectrum. The design gets more advantages of chip area, power, EMI reduction and jitter performance because the design has larger loop bandwidth and simple architecture. In addition, we also adopt the current mode capacitor amplification to save more chip area.

The proposed spread-spectrum clock generator circuit is fabricated in TSMC 40nm 1P9M CMOS process at 6 GHz operating frequency. The supply voltage is 0.9 V. The input reference frequency is 100 MHz. The reduction of electromagnetic interference is 21 dB with the spread-spectrum mechanism modulated by triangular wave. The chip area is 1.11 mm2. The core area is 0.13 mm2.
關鍵字(中) ★ 展頻時脈
★ 時脈
★ 次取樣鎖相迴路
★ 鎖相迴路
關鍵字(英) ★ spread spectrum clock generator
★ clock generator
★ sub-sampling phase-locked loop
★ phase-locked loop
論文目次 目錄
摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第1章 緒論 1
1.1 背景簡介 1
1.2 研究動機 3
1.3 論文架構 4
第2章 展頻時脈產生器概論 5
2.1 電磁干擾的影響與解決方式 5
2.1.1 傳統抑制電磁干擾方式 5
2.1.2 展頻時脈理論 7
2.1.3 展頻時脈的展頻範圍 10
2.1.4 展頻時脈的展頻波種類 12
2.2 展頻時脈產生器電路 14
2.2.1 展頻時脈產生器概略分類 14
2.3 除頻器調變技術 15
2.3.1 挹注電流補償技術 16
2.3.2 相位補償技術 18
2.3.3 近期特殊展頻技術 20
2.4 次取樣鎖相迴路操作 22
2.4.1 鎖相迴路與次取樣鎖相迴路系統架構比較 22
2.4.2 次取樣鎖相迴路的限制與補強方式 24
2.5 總結 26
第3章 展頻時脈產生器系統與電路架構設計 27
3.1 簡介 27
3.2 電路架構 28
3.3 系統分析 31
3.3.1 鎖相迴路系統分析 31
3.3.2 次取樣鎖相迴路系統分析 34
3.4 展頻操作說明 37
3.4.1 展頻原理 37
3.4.2 多工器操作與適應機制設計 39
3.4.3 展頻操作面臨的問題 42
3.4.4 系統行為模擬 45
第4章 展頻時脈產生器子電路設計與模擬分析 46
4.1. 鎖相迴路的子電路設計 46
4.1.1. 相位頻率檢測器 47
4.1.2. 利用電流放大技術的迴路濾波器 48
4.1.3. 電荷幫浦 49
4.1.4. 電壓控制振盪器 52
4.1.5. 除頻器 54
4.1.6. 次取樣相位檢測器 55
4.1.7. 在次取樣鎖相迴路的電荷幫浦 56
4.1.8. 脈波產生器 58
4.1.9. 相位內插器 59
4.2. 模擬結果 60
4.2.1. 操作在6 GHz之次取樣鎖相迴路模擬 61
4.2.2. 次取樣鎖相迴路模擬之操作在6 GHz展頻電路模擬 63
第5章 晶片佈局與量測規劃 65
5.1. 電路佈局 65
5.1.1. 晶片封裝 66
5.1.2. 佈局與電源規劃 69
5.2. 高速輸入輸出與電源I/O的特殊考量 70
5.3. 量測考量 71
5.3.1. 量測環境 71
5.3.2. 高頻輸出緩衝器 72
5.3.3. 低頻輸出緩衝器 74
5.4. 規格比較表 75
第6章 結論 77
6.1. 結論 77
6.2. 未來研究方向 78
參考文獻 79
參考文獻 參考文獻
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指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2019-8-20
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