博碩士論文 105521090 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:20 、訪客IP:3.235.227.117
姓名 詹凱鈞(Kai-Chun Chan)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於C頻段之互補式金氧半導體低相位雜訊C類壓控振盪器暨變壓器耦合四相位壓控振盪器暨利用F類壓控振盪器於C頻段之整數型鎖相迴路暨X頻段III-V族高功率振盪器之研製
(Implementations on C-band CMOS Low Phase Noise Class-C Voltage Controlled Oscillator, Transformer-coupled Quadrature Voltage Controlled Oscillator, C-band Integer-N Phase Locked Loop with Class-F Voltage Controlled Oscillator and X-band III-V Power Oscillators)
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摘要(中) 本論文擬研究收發機中的本地振盪信號電路,設計應用於C頻段以及X頻段的本地振盪電路。論文一共實現六種電路。首先利用tsmcTM 0.18 m 互補式金氧半導體實現C頻段本地振盪電路;接著利用WINTM 0.25 m GaN以及WINTM 0.15 m InGaAs pHEMT兩種III-V族製程實現X頻段高功率本地振盪電路。以下為本次論文所實現之六個電路,主要分為以金氧半導體實現的三種電路以及以III-V族實現的三種電路。
一、應用於C頻段互補式金氧半導體本地振盪電路
1.低相位雜訊C類壓控振盪器
C類控振盪器具有低功耗、高電流效率以及低相位雜訊之特性,文中分析傳統考畢茲振盪器與C類壓控振盪器的相位雜訊,並且提出以動態偏壓使振盪器即使偏壓在C類仍可以穩定起振的方法。電路功耗為3.9 mW,可調頻寬為5.28 - 5.53 GHz(4.62 %),相位雜訊在1 MHz偏移頻率下最低為-120.1 dBc/Hz,達到FoM最高為-188.7,晶片面積為0.671 × 0.909 mm2。
2.變壓器耦合之四相位壓控振盪器
本電路先介紹四相位的需求以及產生方式,並分析變壓器耦合如何產生四相位信號,之後推出利用變壓器耦合所解決的雙模振盪問題,並利用尾濾波技術進一步提升相位雜訊的表現。電路功耗為21.6 mW,可調頻寬為5.23 – 5.73 GHz (9.1 %),相位雜訊在1 MHz偏移頻率下最低為-119.75 dBc/Hz,相位誤差小於4o,達到FoM最高為-180.8,晶片面積為1.132 × 0.738 mm2。
3.利用F類壓控振盪器之整數型鎖相迴路
本電路利用F類壓控振盪器,改善壓控振盪器的相位雜訊,並加入回授網路結合成整數型鎖相迴路,文中分析鎖相迴路所需數學模型,並詳細介紹個子電路之電路架構與運作方式。電路功耗為32.5 mW,相位雜訊在鎖定時10 kHz偏移頻率下最低為-92.6 dBc/Hz 1 MHz偏移頻率下最低為-95.4 dBc/Hz,鎖定時低頻FoM最高達到-192.3,晶片面積為0.887 × 1.077 mm2。
二、應用於X頻段III-V族高功率本地振盪電路
1.克拉普功率振盪器
本電路利用0.25 m GaN高功率製程,實現了克拉普功率振盪器。電路功耗為416 mW,相位雜訊在1 MHz偏移頻率下最低為-118.02 dBc/Hz,輸出功率達到19.6 dBm,換算效率達到21.9 %,利用文獻的電路優化指數FoMPOSC達到-210.9,晶片面積為1.5 × 1 mm2。
2.克拉普功率壓控振盪器
本電路利用0.15 m GaAs,以GaAs等效的二極體當作可變電容,實現了克拉普功率控振盪器,並希望可實現在GaN製程上。電路功耗為20 mW,可調頻寬為9.41 – 10.04 GHz (6.4 %)相位雜訊在1 MHz偏移頻率下最低為-100.55 dBc/Hz,輸出功率達到7.7 dBm,換算效率達到35.6 %,利用文獻的電路優化指數FoMPOSC達到-202.4,晶片面積為1.5 × 1 mm2。
3.利用E類網路之功率振盪器
本電路利用0.25 m GaN高功率製程,設計E類匹配網路,實現了E類網路功率振盪器,並且根據先前下線量測果,估計本次電路的相位雜訊,由於電路尚在製作過程,在此僅提出設計方法以及完整電磁模擬後的模擬結果。電路功耗為2.9 W,相位雜訊在1 MHz偏移頻率下最低為-126.5 dBc/Hz,輸出功率達到30.5 dBm,換算效率達到39.1 %,利用文獻的電路優化指數FoMPOSC達到-232.9,晶片面積為1.5 × 1 mm2。
摘要(英) This thesis developed six local oscillator (LO) circuits for the signal sources of C band and X band transceivers. Three C band LOs were realized in tsmcTM CMOS processes. The X band high power LOs were realized in WINTM 0.25 m GaN and InGaAs pHEMT technologies. The developed LO circuits are listed as follow,
A Implementations on C-band CMOS Local Oscillator Circuits
I.Low Phase Noise Class-C Voltage Control Oscillator
The Class-C oscillator has the features of low power consumption, high current efficiency and low phase noise. This thesis analyzed the phase noise performance of the traditional Colpitts oscillator and Class-C oscillator, repectively. Then, the author proposed a dynamic bias circuit to solve hard start-up problem of the Class-C oscillator. The designed oscillator consumed the dc power of 3.9 mW. The measured tuning range is 5.28 - 5.53 GHz (4.62 %). The lowest phase noise at 1-MHz offset frequency is -120.1 dBc/Hz which is correspondent to the FoM of -188.7. The chip size includes all pads is 0.671 × 0.909 mm2.
II.Transformer Coupled Quadrature Voltage Control Oscillator
The thesis introduced the requirements of the quadrature signal and how to generate the IQ signals by using transformer coupling technique. Meanwhile, the bi-model problem in IQ signal generation can be solved by this technique accordingly. The use of tail filter also improved the phase noise of quadrature oscillator. These IQ signals totally consumed the dc power of 21.6 mW. The tuning range of the circuit is from 5.23 to 5.73 GHz (9.1 %). The lowest phase noise at 1-MHz offset frequency is -119.75 dBc/Hz which is correspondent to a lowest FoM of -180.8. The chip size include all pads is 1.132 × 0.738 mm2.
III.Integer-N Phase Locked Loop (PLL) with Class-F Voltage Controlled Oscillator
The PLL adopted a Class-F VCO to improve the phase noise perforamnce. This thesis analyzed the mathematical model of the PLL and developed all functional block cicruits of the PLL. The PLL consumed the dc power of 32.5 mW. The phase noise at 10-kHz offset frequency as the PLL was locked is -95.4 dBc/Hz, and achieves a low frequency FoM of -192.3. The chip size include all pads is 0.887 × 1.077 mm2.
B.Implementations on X-band III-V High Power Local Oscillator Circuits
I.Clapp Power Oscillator
The Clapp power oscillator circuit was realized in WINTM 0.25 m GaN high power process. Total power consumption of the circuit is 416 mW. The lowest phase noise at 1 MHz offset frequency is -118.02 dBc/Hz. The output power is 19.6 dBm. The DC-RF conversion efficiency is 21.9 %. The FoMPOSC, which adds output power and efficiency performance in the conventional FoM of oscillator, is -210.9. The chip size includes all pads is 1.5 × 1 mm2.
II.Clapp Power Voltage Control Oscillator
The Clapp power voltage control oscillator circuit was realized by 0.15 m InGaAs pHEMT technology. The GaAs equvilent diode was used as a varactor for the frequrncy tuning. The total power consumption is 20 mW. The tuning range is from 9.41 to 10.04 GHz (6.4 %). The lowest phase noise at 1 MHz offset frequency is -100.55 dBc/Hz. The highest output power is 7.7 dBm. The DC-R Fconversion efficiency is 35.6 %. The FoMPOSC is -202.4. The chip size included all pads is 1.5 × 1 mm2.
III.Power Oscillator use Class-E Network
The Class-E power oscillator was realized in 0.25 m GaN high power process. The phase noise was estimated according to the phase noise measured before. Since the circuit is still in the process, the design process and full EM simulation result is shown in this thesis. The expected total power consumption is 2.9 W. The lowest phase noise at 1 MHz offset frequency is estimated as -126.5 dBc/Hz. The highest output power is 30.5 dBm. The DC-RF efficiency 39.1 % was calculated. The FoMPOSC is -232.9. The chip size is 1.5 × 1 mm2.
關鍵字(中) ★ 壓控振盪器
★ 鎖相回路
★ 四相位壓控振盪器
★ 功率振盪器
★ 互補式金氧半導體
★ 氮化鎵
關鍵字(英)
論文目次 摘要 I
Abstract III
誌謝 VI
目錄 VII
圖目錄 IX
表目錄 XIII
第一章 緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節敘述 2
第二章 低雜訊使用動態偏壓之C類壓控振盪器 3
2-1 考畢茲壓控振盪器雜訊分析 3
2-2 C類壓控振盪器電流以及振幅分析 6
2-3 C類壓控振盪器電路設計 9
2-4 量測與模擬結果 13
2-5 結果與討論 19
第三章 變壓器耦合之四相位壓控振盪器 20
3-1 四相位振盪器簡介 20
3-2 尾濾波以及二次諧波抑制簡介 22
3-3 四相位壓控振盪器電路設計 25
3-4 量測與模擬結果 37
3-5 結果與討論 43
第四章 利用F類壓控振盪器於C頻段之整數型鎖相迴路 45
4-1 鎖相迴路基本架構 45
4-2 鎖相迴路迴路分析 51
4-3鎖相迴路電路設計 54
4-3-1 C頻段F類壓控振盪器 55
4-3-2 頻率除頻器 61
4-3-3 全擺幅緩衝器 65
4-3-4 相位頻率比較器 66
4-3-5 充電汞 68
4-3-6 迴路濾波器 71
4-4 量測與模擬結果 73
4-5 結果與討論 79
第五章 X頻段克拉普功率振盪器 81
5-1功率振盪器簡介 81
5-2 穩懋半導體 GaN 0.25 m HEMT製程簡介 82
5-3 克拉普振盪器電路設計 83
5-4 量測與模擬結果 92
5-5 結果與討論 95
第六章 X頻段克拉普功率壓控振盪器 96
6-1 穩懋半導體 InGaAs 0.15 m pHEMT製程簡介 96
6-2 克拉普壓控振盪器電路設計 97
6-3 量測與模擬結果 104
6-4 結果與討論 111
第七章 結論 112
4-1 結論 112
4-2 未來方向 114
附錄 使用E類網路之功率振盪器 115
A-1 使用E類網路之功率振盪器電路設計 115
A-2 模擬結果 123
A-3 結果與討論 125
參考文獻 126
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指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2018-7-30
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