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參考文獻
[1] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. d. Groot, “A 46 μW 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset calibration,” in IEEE Journal of Solid-State Circuits, Vol. 52, No. 2, pp. 423-432, Feb. 2017.
[2] M. Krämer, E. Janssen, K. Doris, and B. Murmann, “A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 64, No. 2, pp. 116-120, Feb. 2017.
[3] C.-C. Liu, M.-C. Huang, and Y.-H. Tu, “A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC,” in IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, pp. 2941-2950, Dec. 2016.
[4] Y. Lim, and M. P. Flynn, “A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 10, pp. 2331-2341, Oct. 2015.
[5] R. Sehgal, F. v. d. Goes, and K. Bult, “A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 7, pp. 1592-1603, Jul. 2015.
[6] J. Lin, D. Paik, S. Lee, M. Miyahara, and A. Matsuzawa, “An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 6, pp. 1399-1411, Jun. 2015.
[7] G. Tretter, M. M. Khafaji, D. Fritsche, C. Carta, and F. Ellinger, “Design and Characterization of a 3-bit 24-GS/s FlashADC in 28-nm Low-Power Digital CMOS,” in IEEE Transactions on Microwave Theory and Technique, Vol. 64, No. 4, pp. 1143-1152, Apr., 2016.
[8] Y. Xu, L. Belostotski, and J. W. Haslett, “A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 11, pp. 2316-2325, Nov. 2014.
[9] P. Ritter, S. L. Tual, B. Allard, and M. Möller, “Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold,” in IEEE Journal of Solid-State Circuits, Vol. 49, No. 9, pp. 1886-1894, Sep. 2014.
[10] B. V. Hieu, S. Beak, S. Choi, J. Seon, and T. T. Jeong, “Thermometer-to-binary Encoder with Bubble Error Correction (BEC) Circuit for Flash Analog-to-Digital Converter (FADC),” in IEEE International Conference on Communications and Electronics, pp. 102-106, Nha Trang, Vietnam, Aug. 2010.
[11] Y.-J. Chuang, H.-H. Ou, and B.-D. Liu, “A Novel Bubble Tolerant Thermometer-to-Binary Encoder for Flash A/D Converter,” in IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), pp. 315-318, Hsinchu, Taiwan, Apr. 2005.
[12] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, “Fat Tree Encoder Design for Ultra-High Seed Flash A/D Convertors,” in IEEE the 45th Midwest Symposium on Circuits and Systems (MWSCAS), Vol. 2, pp. II-87-II-90, Tulsa, Oklahoma, Aug. 2002.
[13] B. Xu, Y. Zhou, and Y. Chiu, “A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS,” in IEEE Journal of Solid-State Circuits, Vol. PP, No. 99, pp. 1-10, Jan. 2017.
[14] B. T. Reyes, R. M. Sanchez, A. L. Pola, and M. R. Hueda, “Design and Experimental Evaluation of a TimeInterleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems,” in IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. PP, No. 99, pp. 1-12, Dec. 2016.
[15] C.-Y. Lin and T.-C. Lee, “A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique,” in IEEE Journal of Solid-State Circuits, Vol. 63, No. 7, pp. 929-938, Jun. 2016.
[16] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13 μm CMOS Switched Cascode Track-and-Hold Amplifier,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 7, pp. 512-516, Jul., 2010.
[17] S. Yamanaka, K. Sano, and K. Murata, “A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology,” in IEEE Transactions on Microwave Theory and Technique, Vol. 58, No. 9, pp. 2334-2339, Sep., 2010.
[18] H.-G. Wei, U-F. Chio, Y. Zhu, S.-W. Sin, S.-P. U, and R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 1, pp. 16-20, Jan., 2010.
[19] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 40 Gsamples/s InP-DHBT Track-&-Hold Amplifier,” in IEEE The 5th European Microwave Integrated Circuits Conference, pp. 61-64, Paris, France, Sep., 2010.
[20] Y. Borokhovych, J. C. Scheytt, “10 GS/s 8-bit bipolar THA in SiGe technology,” in IEEE NORCHIP, pp. 1-4, Lund, Sweden, Nov., 2011.
[21] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, M. Riet, J. Godin, and G. Pailler, “A 50-GHz small signal bandwidth 50 GSa/s Track&Hold Amplifier in InP DHBT technology,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, Montreal, Canada, Jun., 2012.
[22] H.-L. Chen, S.-C. Cheng, and B.-W. Chen, “A 5-GS/s 46-dBc SFDR Track and Hold Amplifier,” in IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPAC), pp. 636-639, New Taipei City, Taiwan, Nov., 2012.
[23] M. Macedo, G. W. Roberts, and I. Shih, “Track and hold for Giga-sample ADC applications using CMOS technology,” in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2725-2728, Seoul, South Korea, May, 2012.
[24] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, and J. Godin, “A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology,” in IEEE 20th Telecommunications Forum (TELFOR), pp. 502-505, Belgrade, Serbia, Nov., 2012.
[25] G. Tretter, D.Fritsche, C. Carta, and F. Ellinger, “10-GS/s Track and Hold Circuit in 28 nm CMOS,” in IEEE International Semiconductor Conference Dresden - Grenoble (ISCDG), pp. 1-3, Dresden, Germany, Sep., 2013.
[26] S. Daneshgar, Z. Griffith, M. Seo, and M. J. W. Rodwell, “Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 49, No. 10, pp. 2114-2126, Oct., 2014.
[27] S. Ma, L. Wang, H. Yu, and J. Ren, “A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS,” in IEEE Transactions on Microwave Theory and Technique, Vol. 62, No. 12, pp. 3500-3511, Dec., 2014
[28] H. Aggrawal, and A. Babakhani, “A 40GS/s Track-and-Hold Amplifier with 62dB SFDR3 In 45nm CMOS SOl,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, Tampa Bay, USA, Jun., 2014.
[29] D. Lal, M. Abbasi, and D. S. Ricketts, “A Compact, High Linearity 40GS/s Track-and-Hold Amplifier in 90nm SiGe Technology,” in IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, San Jose, USA, Sep, 2015.
[30] Y.-C. Liu, H.-Y. Chang, S.-Y. Huang, and K. Chen, “Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers,” in IEEE Transactions on Microwave Theory and Technique, Vol. 63, No. 9, pp. 2841-2853 Sep., 2015.
[31] K. N. Madsen, T. D. Gathman, S. Daneshgar, T. C. Oh, J. C. Li, and J. F. Buckwalter, “A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 11, pp. 2692-2702, Nov. 2015.
[32] Y.-A. Lin, Y.-C. Yeh, Y.-C. Liu, and H.-Y. Chang, “A 55-dB SFDR 16-GS/s track-and-hold amplifier in 0.18 μm SiGe using differential feedthrough cancellation technique,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-4, San Francisco, USA, May 2016.
[33] G. Tretter, D. Fritsche, M. Mahdi Khafaji, C. Carta, and F. Ellinger, “A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 63, No. 3, pp. 229-233, MAR. 2016.
[34] K. Vasilakopoulos, A. Cathelin, P. Chevaliert, T. Nguyen and S.P. Voinigescu, “A l08GS/s Track and Hold Amplifier with MOS-HBT Switch,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-4, San Francisco, USA, May 2016.
[35] A. Meyer, P. Desgreys, H. Petit, B. Louis, and R. Corbiere, “Single-ended/differential 2.5-GS/s Double Switching Track-and-Hold Amplifier with 26GHz Bandwidth in SiGe BiCMOS Technology,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, San Francisco, USA, May 2016.
[36] A. Moriyama, S. Taniyama, and T. Waho, “A Low-Distortion Switched-Source-Follower Track-and-Hold Circuit,” in IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 105-108, Seville, Spain, Dec. 2012.
[37] Y.-C. Liu, H.-Y. Chang, and K. Chen, “A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range,” in IEEE MTT-S Int. Microw. Symp. Dig., Florida, USA, June 2014
[38] X. Li, W. L. Kuo, Y. Lu, R. Krithivasan, J. D. Cressler, and A. J. Joseph, “A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier,"in IEEE Compound Semiconductor Integrated Circuit Symposium, Nov. 2005, pp. 105-108.
[39] E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed amplification,” in Proc. I.R.E., vol. 36, Aug. 1948, pp. 956–969.
[40] Seong-Kyun Kim, S. Daneshgar, A. D. Carter, Myung-Jun Choe, M. Urteaga and M. J. W. Rodwell, "A 30 GSample/s InP/CMOS sample-hold amplifier with active droop correction," 2016 IEEE MTT-S International Microwave Symposium (IMS), San Francisco, CA, 2016, pp. 1-4
[41] B. Razavi, Principles of Data Conversion System Design, Willey-IEEE Press, 1994.
[42] G. Tretter, D. Fritsche, C. Carta and F. Ellinger, “Enhancing the Input Bandwidth of CMOS Track and Hold Amplifiers,” in IEEE 20th Microwaves, Radar, and Wireless Communication (MIKON), pp. 1-4, GDAŃSK, Poland, Jun. 2014.
[43] P. Wambacq and W. M. Sansen, Distortion Analysis of Analog Integrated Circuits. Boston, MA, USA: Kluwer Academic, 1998.
[44] P. G. Fonstad, Microelectronic Devices and Circuits. 2006 Electronic Edition.
[45] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuit, 2nd ed. Cambridge, UK. Cambridge University Press, 2004.
[46] B. Razavi, RF Microelectronics, Prentice Hall, 2011.
[47] P. V. Tesla, C. Carta, and F. Ellinger,“Analysis an Design of a 220-GHz Wideband SiGe BiCMOS Distributed Active Combiner,” in IEEE Transactions on Microwave Theory and Technique, vol. 64, no. 10, pp. 3049-3059, Oct. 2016.
[48] S.-H. Chen, “Dual-gate Device Modeling and Microwave/Millimeter-Wave Distributed Amplifier Design,” Master thesis, National Central University, Zhongli, Taoyuan, Taiwan, 2012.
[49] Sonnet User’s Guide, 12th ed. North Syracuse, NY: Sonnet Softw.Inc., 2009.
[50] Y. Li, W.-L. Goh and Y.-Z. Xiong, “A 2 to 92 GHz Distrubuted Amplifier Using 70-nm InP HEMTs,” in IEEE Wireless Symposium (IWS), Shenzhen, China pp.1-4, Mar. 2015.
[51] C.-L. Ler, A. K. b. A’ain, and A. V. Kordesch, “Compact, High-Q, and Low-Current Dissipation CMOS Differential Active Inductor”, IEEE Microwave and Wireless Component Letters, Vol. 18, No. 10, pp. 381-382, Oct. 2008.
[52] 林俞安,使用砷化鎵矽化鍺金氧半場效應電晶體之高速高線性度高解析度追蹤保持放大器,國立中央大學電機工程研究所碩士論文,民國106年。
[53] 黃冠霖,使用矽基製程之低改變率高速寬頻追蹤保持放大器電路,國立中央大學電機工程研究所碩士論文,民國107年。
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