參考文獻 |
[1] Ian Hardcastle, Steve Melvin, James Mayock, Andrew Collar, Paul Simpson, Mike Brookbanks, Ian Bisby, “30 GHz (Ka-band) VSAT DVB-RCS mixer-driver multifunction MMIC,” 2007 European Microwave Conference, Oct. 2007, pp. 1213–1216.
[2] Ja-Yol Lee, Kwidong Kim, Seung-Chul Lee, Jong-Kee Kwon, Jongdae Kim, Sang-Heung Lee, “A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications, ”IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Jul. 2007, pp. 233-236.
[3] Frank Herzel, Sabbir A. Osmany, Klaus Schmalz, Wolfgang Winkler, J. Christoph Scheytt, Thomas Podrebersek, Rudiger Follmann, Heinz-Volker Heyer, “An Integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Jun. 2009, pp. 329-332.
[4] Zhiwei Xu, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Mau-Chung Frank Chang, “A70–78-GHz Integrated CMOS Frequency Synthesizer for W-Band Satellite Communications,” IEEE Trans. Microw. Theory Tech., Oct. 2011, pp. 3206-3218.
[5] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7 , pp.1606-161, Jul. 2011.
[6] T. Musch, “A high precision 24-GHz FMCW radar based on a fractional-N ramp-PLL, ” in IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 2 , pp. 324-327, Apr. 2003.
[7] M. Klotz and H. Rohling, “24 GHz radar sensors for automotive applications, ” 13th International Conference on Microwaves, Radar and Wireless Communications. MIKON - 2000. Conference Proceedings (IEEE Cat. No.00EX428), Aug. 2002, pp. 359-362.
[8] B. Afshar and A. M. Niknejad, “A robust 24 mW 60 GHz receiver in 90 nm standard CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 182–183.
[9] A. Arbabian, S. Kang, S. Callender, J.-C. Chien, B. Afshar, and A.Niknejad, “A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition,” IEEEInt. Symp. on VLSI Design, Automation and Test, Jun. 2012, pp. 56-57.
[10] A. Arbabian, S. Callender, S. Kang, M. Rangwala, and A. Niknejad, “A 94 GHz mm-wave-to-baseband pulsed-radar transceiver with applications in imaging and gesture recognition,” IEEE J. Solid-State Circuits, vol. 48, no. 4, Apr. 2013, pp. 1055–1071.
[11] K. Kang, F. Lin, D.-D. Pham, J. Brinkhoff, C.-H. Heng, Y. X. Guo, and X. Yuan, “A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, Sep. 2010, pp. 1720–1731.
[12] A. Arbabian, S. Callender, S. Kang, B. Afshar, J.-C. Chien, and A.Niknejad, “A 90 GHz hybrid switching pulsed-transmitter for medicalimaging,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2667–2681, Dec. 2010.
[13] J. Lee, M. Liu, and H. Wang, “A 75-GHz PLL in 90-nm CMOS Technology, ” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008.
[14] K.-H. Tsai, and S.-I. Liu, “A 43.7mW 96GHz PLL in 65nm CMOS, ” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 276-277.
[15] C. Lee and S.-I. Liu, “A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers, Feb. 2007, pp. 196-596.
[16] H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, and R. Fujimoto, “A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS,” Proc. Eur. Solid State Circuits Conf., Sep. 2007, pp. 472-475.
[17] K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66GHz quadrature PLL in 45nm digital CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 494-495.
[18] C. Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu, “A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 404-408, May 2008.
[19] K.-H. Tsai, and S.-I. Liu, “A 62–66.1GHz phase-locked loop in 0.13 μm CMOS technology,” IEEE Int. VLSI Design, Automation and Test, Apr. 2008, pp.113-116.
[20] H.-K. Chen, T. Wang, and S.-S. Lu, “A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, May 2011, pp. 1327-1338.
[21] S. Kang, J.-C. Chien, and A. M. Niknejad, “A 100GHz phase-locked loop in 0.13µm SiGe BiCMOS process,” Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2011, pp.1-4.
[22] S. Shahramian, A. Hart, A. Tomkins, A. C. Carusone, P. Garcia, P. Chevalier, and S. P. Voinigescu, “Design of a Dual W- and D-Band PLL,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1011-1022, May 2011.
[23] K.-H. Tsai, and S.-I. Liu, “A 104-GHz phase-locked loop using a VCO at second pole frequency,” IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, pp. 80-88, Jan. 2012.
[24] B.-Y. Lin and S.-I. Liu, “A 132.6-GHz phase-locked loop in 65 nm digital CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 58, no. 10, pp. 617-621, Oct. 2011.
[25] T.-Y. Chang, C.-S. Wang, and C.-K. Wang, “A low power W-band PLL with 17-mW in 65-nm CMOS technology,” Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2011, pp. 81-84.
[26] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
[27] G. Reddy Gangasani, P. Kinget, “Injection-lock dynamics in non-harmonic oscillators,” Circuits and Systems 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, pp. 4 pp.-1678.
[28] A. Mirzaei and H. Darabi, “Mutual pulling between two oscillators,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 360–372, Feb. 2014.
[29] H. Jia, L. Kuang, Z. Wang, and B. Chi, “A W-band injection-locked frequency doubler based on top-injected coupled resonator,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 1, pp. 210–218, Jan. 2016.
[30] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “Injection-locked CMOS frequency doublers for μ-Wave and mm-Wave applications,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1565–1574, Aug. 2010.
[31] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “A 6 mW 115 GHz CMOS injection-locked frequency doubler with differential output,” Proc. Int. Conf. IC Design and Technology (ICICDT), Jun. 2010, pp. 236–239.
[32] A. Mazzanti, E. Monaco, M. Pozzoni, F. Svelto “A 13.1% Tuning Range 115GHz Frequency Generator Based on Injection-Locked Frequency Doubler in 65nm CMOS”, IEEE International Solid-State Circuits Conference, Feb. 2010, pp. 422–423.
[33] C. Leifso and J. Nisbet, “A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 405–412, Feb. 2006.
[34] Z. Chen and P. Heydari, “An 85–95.2 GHz transformer-based injection-locked frequency tripler in 65-nm CMOS,” IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 776–779.
[35] Y. Yeh and H. Chang, “A W-band wide locking range and low dc power injection-locked frequency tripler using transformer coupled technique,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 2, pp. 860–870, Feb. 2013.
[36] W. K. Chan and J. R. Long, “A 56–65 GHz injection-locked frequency tripler with quadrature outputs in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739–2746, Dec. 2008.
[37] S.-W. Tam, E. Socher, A. Wong, Y. Wang, L. D. Vu, and M.-C. F. Chang, “Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2008, pp. 131–134.
[38] C.-N. Kuo and T.-C. Yan, “A 60 GHz injection-locked frequency tripler with spur suppression,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 10, pp. 560–562, Oct. 2010.
[39] M.-C. Chen and C.-Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869–1878, Aug. 2008.
[40] Y.-L. Yeh, C.-S. Huang, and H.-Y. Chang, “A 20.7% locking range W-band fully integrated injection-locked oscillator using 90 nm CMOS technology,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 1-3.
[41] N. M. and E. S., “Analysis and Design of an X-Band-to-W-Band CMOS Active Multiplier with Improved Harmonic Rejection,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 5, pp. 1924–1933, Feb. 2013.
[42] C.-C. Wang, Z. Chen, and P. Heydari, “W-band silicon-based frequency synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1307–1320, May. 2012.
[43] F.-H. Huang and Y.-M. Hsin, “A V-band frequency tripler with output power enhancement in 90 nm CMOS,” in Proc. 4th Int. HSIC, May. 2012, pp. 1–4.
[44] N. Mazor, O. Katz, B. Sheinman, R. Carmon, R. Ben-Yishay, R. Levinger, A. Bruetbart, and D. Elad, “A high suppression frequency tripler for 60-GHz transceivers,” in Proc. IEEE MTT-S Int. Dig., May. 2015, pp. 1–4.
[45] Y.-A. Lin, T.-H. Lin, and H.-Y. Chang, “A 42–71 GHz 90 nm CMOS injection-locked voltage-controlled oscillator using bulk injection technique,” in Proc. Eur. Microw. Integr. Circuits Conf., Sep. 2015, pp. 108–111.
[46] K. Kamogawa, T. Tokumitsu, and I. Toyoda, “A 20-GHz-band subharmonically injection-locked oscillator MMIC with wide locking range,” IEEE Microw. Guided Wave Lett., vol. 7, no. 8, pp. 233–235, Aug. 1997.
[47] F.-H. Huang, C.-K. Lin, and Y.-J. Chan, “V-band GaAs pHEMT cross-coupled sub-harmonic oscillator,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 8, pp. 473–475, Aug. 2006.
[48] L. Ye, H. Liao, and R. Huang, “A CMOS W-band ×4 frequency multiplier with cascading push-pull frequency doublers,” in Proc. Asia–Pacific Microw. Conf., 2012, pp. 166–168.
[49] Yu-Sheng Lin, Cheng-Han Wu, Chun-Chi Su, Yeong-Her Wang, “A Low-Power K-Band Frequency Quintupler with Current-Reused and Harmonic-Enhanced Technique”, IEEE Microw. Wireless Compon. Lett., vol. 24, no. 10, pp. 701-703, Oct. 2014.
[50] I. Kallfass, H. Massler, A. Tessmann, A. Leuther, M. Schlechtweg, and G. Weimann, “A broadband frequency sixtupler MIMIC for the W-band with > 7 dBm output power and > 6 dB conversion gain,” in IEEE Int. MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 2169–2172.
[51] U. J. Lewark, A. Tessmann, H. Massler, A. Leuther, and I. Kallfass, “Active single ended frequency multiplier-by-nine MMIC for millimeter-wave imaging applications,” in Proc. Wkshp. Integr. Nonlinear Microw. Millimetre-Wave Circuits, Apr. 2011, pp. 1–4.。
[52] N. Mazor and E. Socher, “X-band to W-band frequency multiplier in 65 nm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 8, pp. 424–426, Aug. 2012.
[53] C.-C. Wang, Z. Chen, and P. Heydari, “W-Band silicon-based frequency synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1307-1320, May 2012.
[54] L. Ye, Y. Wang, C. Shi, H. Liao, and R. Huang, “A W-band divider-less cascading frequency synthesizer with push-push ×4 frequency multiplier and sampling PLL in 65nm CMOS,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp.1-3.
[55] A. Tang, D. Murphy, G. Virbila, F. Hsiao, S.-W. Tam, H.-T. Yu, H.-H. Hsieh, C.-P. Jou, Y. Kim, A. Wong, A. Wong, Y.-C. Wu, and M.-C. F. Chang, “D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp.1-3.
[56] G. Liu, A. Trasser, and H. Schumacher, “A 64–84-GHz PLL with low phase noise in an 80-GHz SiGe HBT technology,” IEEE Trans Microw. Theory Tech., vol. 60, no. 12, pp. 3739-3748, Dec. 2012.
[57] A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, “A low phase noise quadrature injection locked frequency synthesizer for mm-wave applications,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp.2635-2649, Nov. 2011.
[58] C.-Y. Wu, M.-C. Chen, and Yi-Kai Lo, “A phase-locked loop with injection-locked frequency multiplier in 0.18-µm CMOS for V-Band applications,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1629-1636, Jul. 2009.
[59] C.-L. Wei, T.-K. Kuan, and S.-I. Liu, “A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 62, no. 6, pp. 548-552, Jun. 2015.
[60] Y. C. Huang and S. I. Liu, “A 2.4 GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417–428, Feb. 2013.
[61] F. Liang and K. J. Hsiao, “An injection-locked ring PLL with self-aligned injection window,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. 90–92.
[62] P.-H. Feng, and S.-H. Liu, “A Current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1523-1532, Apr. 2013.
[63] Y.-L. Yeh, S.-Y. Huang, Y.-E. Shen, and H.-Y. Chang, “A 90 nm CMOS low phase noise sub-harmonically injection-locked voltage-controlled oscillator with FLL self-alignment technique,” IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, USA, May 2016, pp. 1–4.
[64] Hong-Yeh Chang, Chun-Ching Chan, Ian Yi-En Shen, Yen-Liang Yeh, Shu-Yan Huang, “Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique”, IEEE Trans. Microw. Theory Tech., vol. 64, pp. 4632-4645, 2016.
[65] B. Razavi, RF Microelectronics, Prentice-Hall, 1998.
[66] 高曜煌,射頻鎖相迴路IC設計,第二章,滄海書局,民國94年。
[67] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed MilimeterWave Wireless Systems,” IEEE ICCSC 2008, pp. 812-815.
[68] F. Maloberti and M. Signorelli, “Quadrature Waveform Generator with Enhanced Performances,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 222-226, 1998.
[69] 劉深淵、楊清淵,鎖相迴路,滄海書局,民國100年。
[70] N. D. Dalt, S. Deksen, P. Greco, C. Sandner, H. Schmid, and K. Strohmayer, “A fully integrated 2.4 GHz LC-VCO frequency synthesizer with 3 ps jitter in 0.18 µm digital standard CMOS copper technology,” Proc. Eur. Solid-State Device Research Conf., Sep. 2002, pp. 415-418.
[71] H.-Y. Chang, Y.-H. Cho, M.-F. Lei, C.-S. Lin, T.-W. Huang, and H. Wang, “A 45-GHz quadrature voltage controlled oscillator with a reflection-type IQ modulator in 0.13-m CMOS technology,” IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2006, pp. 739-742.
[72] S. Ko, J.-G. Kim, T. Song, E. Yoon, and S. Hong, “20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers,” in IEEE RFIC Symp. Dig., Jun. 2004, pp. 269–272.
[73] M. Hossain and A. Chan Carusone,“20 GHz low power QVCO and de-skew techniques in 0.13-m digital CMOS,” IEEE Custom Integrated Circuits Conf., 2008, pp. 447-450.
[74] S. Hackl, J. Bock, G. Ritzberger, M. Wurzer, and A. L. Scholtz “A 28-GHz monolithic integrated quadrature oscillator in SiGe Bipolar Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135-137, Jan. 2003.
[75] W. L. Chan, H. Veenstra, and J. R. Long, “A 32GHz quadrature LC-VCO in 0.25μm SiGe BiCMOS technology,” 2005 Int. Solid-State Circuit Conf. Dig., San Francisco, USA, Mar. 2005 pp. 538-539.
[76] C.-H. Lin and H.-Y. Chang, “A low phase noise low DC power quadrature voltage-controlled oscillator using a 0.18-m CMOS process,”Proc. EuMIC, Sept. 2009, pp. 28-29.
[77] C.-L. Yang and Y.-C. Chiang, “Low phase-noise low-power CMOS VCO constructed in current-reused configuration,” IEEE Microw. and Wireless Compon. Lett., vol. 18, no. 2, pp. 136-138, Feb. 2008.
[78] H.-Y. Chang, and Y.-T. Chiu, “K-band CMOS differential and quadrature voltage-controlled oscillators for low phase-noise and low-power applications,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 46–59, Jan. 2012.
[79] S.-Y. Lee and C.-Y. Chen, “Analysis and Design of a wide-tuning-range VCO with quadrature outputs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1209-1213, Dec. 2008.
[80] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 873-887, Jun. 2001.
[81] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, Dec. 2002.
[82] C.-H. Lin, and H.-Y. Chang, “A low-phase-noise CMOS quadrature voltage-controlled oscillator with self-injection-coupled technique,” IEEE Transactions on Circuit and System II, Exp. Briefs. vol. 59, no. 10, pp. 623-627, Oct. 2012.
[83] 林紀賢,注入鎖定非線性單晶微波積體電路之研究,國立中央大學電機工程研究所博士論文,民國101年。
[84] 邱垣達,低功耗低相位雜訊差動及四相位單晶片微波積體電路壓控振盪器之研究,國立中央大學電機工程研究所碩士論文,民國100年。
[85] 呂冠學,微波及毫米波倍頻器、多相位高功率高效率壓控振盪器及鎖相迴路之研製,國立中央大學電機工程研究所碩士論文,民國105年。
[86] S. Jeon, A. Suarez and D. B. Rutledge, “Nonlinear design technique for high power switching mode oscillators,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 10, pp. 3630-3640, Oct. 2006.
[87] H.-Y. Chang, C.-C. Chan, S.-M. Li, H.-N. Yeh, I. Y.-E. Shen, and G.-L. Huang, “Design and analysis of CMOS low phase noise low quadrature error V-band sub-harmonically injection-locked quadrature FLL,” IEEE Trans. Microw. Theory Tech., vol. 66, no. 06, pp. 2851-2866, Jun. 2018.
[88] K. M. Johnson, “Large Signal GaAs MESFET oscillator design,” IEEE Trans. Microw. Theory Tech., vol. 27, no. 3, pp. 217-227, Mar. 1979.
[89] G Gonzalez , Microwave Transistor Amplifiers Analysis and Design , Prentice Hall, 1997.
[90] H. S. Choi, Q. D. Bui, and C.-S. Park, “A Low-Power CMOS VCO for 2.4GHz WLAN,” Compound Semiconductor Integrated Circuit Symposium, 2007. CSIC 2007. IEEE, Oct. 2007, pp. 1–4.
[91] J. Yang, C. Kim, D. Kim, and S. Hong, “Design of a 24 GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 173–177, Mar. 2010.
[92] Sonnet Software Inc., Sonnet User’s Manual, Release 13, North Syracuse, NY, Jun. 2011.
[93] Majid Jalalifar and Gyung-Su Byun, “A Current-Reused Back-Gate Coupling QVCO Using Transformer Feedback Structure,” IEEE Microw. and Wireless Compon. Lett., vol. 26, no.7,pp. 534-536, Jul. 2016.
[94] T. D. Loveless, S. Jagannathan, E. X. Zhang, D. M. Fleetwood, J. S. Kauppila, T. D. Haeffner, L. W. Massengill, “Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology,” IEEE Transactions on Nuclear Science, vol. 64, no. 1, pp. 204-211, Jan. 2017.
[95] S. Saberi and J. Paramesh, “A 11.5–22 GHz dual-resonance transformer-coupled quadrature VCO,” Proc. IEEE RFIC, 2011, pp. 1–4.
[96] M.-H. Li, Y.-H. Liao, and H.-Y. Chang, “A K-band low power high accuracy quadrature VCO using gate-modulated coupling and transformer feedback technique,” Proc. Asia Pacific Microw. Conf., 2014, pp. 895–897.
[97] H.-Y. Chang and Y.-T. Chiu, “K-band CMOS differential and quadrature voltage-controlled oscillators for low phase-noise and low-power applications,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 1, pp. 46–59, Jan. 2012.
[98] Chi-Hsien Lin, Yu-Cheng Liu, Yen-Liang Yeh, Han-Chi Chiu, and Hong-Yeh Chang, “A 60-GHz low dc power self-injection coupling CMOS quadrature voltage-controlled oscillator with high quadrature accuracy,” IEEE MTT-S International Microwave Symposium Digest (MTT), Seattle, WA, Jun. 2013, pp. 1-3.
[99] N.-C. Kuo, J.-C. Chien, and A. Niknejad, “Design and analysis on bidirectionally and passively coupled QVCO with nonlinear coupler,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4, pp. 1130–1141, Apr. 2015.
[100] P.-Y. Wang, Y.-C. Chang, K.-H. Chuang, D.-C. Chang, and S. S. H. Hsu, “A low phase-noise 24 GHz CMOS quadrature-VCO using PMOS source-follower coupling technique,” in Proc. Euro. Microw. Conf., pp. 572–575, 2014.
[101] W. L. Chan, J. R. Long, “A 56-to-65 GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90-nm CMOS”, IEEE J. of Solid-State Circuits, Vol. 43, no. 12, pp. 2739-2746, Dec. 2008.
[102] A. Musa et al., “A 58-63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS,” A-SSCC Dig. Tech. Papers, Nov. 2010, pp.189-192.
[103] G. Mangraviti, “A 52-66GHz Subharmonically Injection-Locked Quadrature Oscillator with 10 GHz Locking Range in 40nm LP CMOS,” RFIC Symposium, Jun. 2012, pp. 309–312.
[104] A. E. Sieman, Lasers, CA: University Science Books, 1986.
[105] R. R. Ward, The living Clocks, New York: Alfred Knopf, 1971.
[106] C. Mao, C. S. Nallani, S. Sankaran, E. Seok, and K. K. O, “125-GHz diode frequency doubler in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1531-1538, May. 2009.
[107] Y. Lee, J. R. East, and L. P. B. Katehi, “High efficiency W-band GaAs monolithic frequency multipliers,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 529-535, Feb. 2004.
[108] 李哲誠,高效率功率放大器與振盪器研製,國立中央大學電機工程研究所碩士論文,民國102年。
[109] U. R. Pferiffer, C.Mishra, R. M. Rassel, S. Pinkett, and S. K. Reynolds, “Schottky barrier diode circuits in silicon for future millimeter-wave and Terahertz applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 364-371, Feb. 2008.
[110] 廖彥涵,微波毫米波寬頻振盪器與鎖相迴路之研製,國立中央大學電機工程研究所碩士論文,民國102年。
[111] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5–10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862–1872, Nov. 2004.
[112] L.-C. Cho, C. Lee, and S.-I. Liu, “A 1.2-V 37-38-GHz eight-phase clock generator in 0.13-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 42, pp. 1261-1270, Jun. 2007.
[113] S. Kang et al., “A W-band low-noise PLL with a fundamental VCO in SiGe for millimeter-wave applications,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 10, pp. 2390–2404, Oct. 2014.
[114] 葉彥良,應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究,國立中央大學電機工程研究所博士論文,民國102年。
[115] C.-S. Lin, P.-S. Wu, M.-C. Yeh, J.-S. Fu, H.-Y. Chang, K.-Y. Lin, and H. Wang, “Analysis of multiconductor coupled-line Marchand baluns for miniature MMIC design,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 6, pp. 1190-1199, Jun. 2007.
[116] Y.-G. Kim, K. W. Kim, and Y.-K. Cho, “A planar ultra-wideband balanced doubler,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 1243-1246.
[117] R. Bitzer, “Planar broadband MIC balanced frequency doublers,” in IEEE MTT-S Int. Microw. Symp. Dig., vol. 1, no. 7, pp. 273-276, Jul. 1991.
[118] S. A. Maas and Y. Ryu, “A broadband, planar, monolithic resistive frequency doubler,” in IEEE MTT-S Int. Microw. Symp. Dig., vol. 1, no. 5, pp. 443-446, May. 1994.
[119] Bryllert, A. Malko, J. Vukusic, and J. Stake, “A 25-75 GHz miniature double balanced frequency doubler in 0.18-μm CMOS Technology,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 4, pp. 275-277, Apr. 2008.
[120] D. Shim, C. Mao, S. Sankaran, and K. K. O, “150 GHz complementary anti-parallel diode frequency tripler in 130 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 1, pp. 43-45, Jan. 2011.
[121] T. Kiuru, J. Mallat, A. V. Räisänen, and T. Närhi, “Compact broadband MMIC Schottky frequency tripler for 75–140 GHz”, in Proc. Eur. Micro. Integr. Circuits Conf., Oct. 2011, pp. 108-111
[122] Y. Wang, W. L. Goh, Y.-Z. Xiong, “A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS,” in IEEE Int. Solid-State Circuits Conf., Tech. Dig., Feb. 2012, pp. 262-264.
[123] Y. Campos-Roca, C. Schwörer, A. Leuther, and M. Seelmann-Eggebert, “G-band metamorphic HEMT-based frequency multiplier,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 7, pp. 2893–2992, Jul. 2006.
[124] A. Boudiaf, D. Bachelet, and C. Rumelhard, “A high-efficiency and low-phase-noise 38 GHz pHEMT MMIC tripler,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2546–2553, Dec. 2000.
[125] J. C. Chiu, C. P. Chang, M. P. Houng, and Y. H.Wang, “A 12–36 GHz PHEMT MMIC balanced frequency tripler,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 1, pp. 19–21, Jan. 2006.
[126] Y. Campos-Roca, L. Verweyen, M. Fernández-Barciela, E. Sánchez, M. C. Currás-Francos, W. Bronner, A. Hülsmann, and M. Schlechtweg, “An optimized 25.5–76.5 GHz PHEMT-based coplanar frequency tripler,” IEEE Microw. Guided Wave Lett., vol. 10, no. 6, pp. 242–244, Jun. 2000.
[127] N.-C. Kuo, Z.-M. Tsai, K. Schmalz, J. C. Scheytt, and H. Wang, “A 52-75 GHz frequency quadrupler in 0.25-µm SiGe BiCMOS process”, Proc. Eur. Micro. Integr. Circuits Conf., Sep. 2010, pp. 365-368.
[128] E. Öjefors, B. Heinemann and U. R. Pfeiffer, “A 325 GHz Frequency Multiplier Chain in a SiGe HBT Technology,” Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., May. 2010, pp. 91-94.
[129] E. Öjefors, B. Heinemann, and U. R. Pfeiffer, “Active 220- and 325-GHz frequency multiplier chains in an SiGe HBT technology,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1311-1318, May. 2011.
[130] J.-H. Chen, and H. Wang, “A high gain, high power K-band frequency doubler in 0.18 μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 9, pp. 522-524, Sep. 2010.
[131] K. Y. Lin, J. Y. Huang, and S. C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Mircow. Wireless Compon. Lett., vol. 19, no. 5, pp. 308-310, May. 2009.
[132] K. Yamamoto, “A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique,” IEEE J. Solid State Circuits, vol. 40, no. 6, pp. 1288-1295, Jun. 2005.
[133] N.-C. Kuo, J.-C. Kao, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 60-GHz frequency tripler with gain and dynamic-range enhancement,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp. 660-671, Mar. 2011.
[134] U. J. Lewark, A. Tessmann, H. Massler, S. Wagner, A. Leuther, and I. Kallfass, “300 GHz active frequency-tripler MMICs,” in Proc. Eur. Micro. Integr. Circuits Conf., Sep. 2011, pp. 236-339.
[135] D. Shin, S. Park, S. Raman and K. J. Koh, “A subharmonically injection-locked PLL with 130 fs RMS jitter at 24 GHz using synchronous reference pulse injection from nonlinear VCO envelope feedback, ” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 100-103.
[136] S. Kishimoto, K. Maruhashi, M. Ito, T. Morimoto, Y. Hamada, and K. Ohata, “A 60-GHz-band subharmonically injection locked VCO MMIC operating over wide temperature range,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2005, pp. 1689–1692.
[137] K. Kamogawa, T. Tokumitsu, and M. Aikawa, “Injection-locked oscillator chain: A possible solution to millimeter-wave MMIC synthesizers,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 9, pp. 1578–1584, Sep. 1997.
[138] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649–1658, Aug. 2007.
[139] C.-K. Hsieh, K.-Y. Kao, J. R. Tseng, and K.-Y. Lin, “A K-band CMOS low power modified Colpitts VCO using transformer feedback,” in IEEE MTT-S Int Microw. Symp. Dig., Jun. 2009, pp. 1293–1296.
[140] 葉瀚濃,使用注入鎖定技術之W頻段除三除頻器與V頻段除六除頻器及Q頻段鎖頻迴路,國立中央大學電機工程研究所碩士論文,民國107年。
[141] J. Lee, and H. Wang, "Study of subharmonically injection-locked PLLs," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May. 2009.
[142] S. Hackl, J. Bock, G. Ritzberger, M. Wurzer, and A. L. Scholtz “A 28-GHz monolithic integrated quadrature oscillator in SiGe Bipolar Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135-137, Jan. 2003.
[143] Fredrik Tillman, Niklas Troedsson and Henrik Sjöland, “A 1.2 volt 1.8GHz CMOS quadrature front-end,” Symp. VLSI Circuits Dig. Tech., Jun. 2004, pp. 362–365.
[144] A. Rofougaran, J. Rael, M. Rofougaran, A. Abidi, “A 900 MHz LC-oscillator with quadrature outputs,” IEEE Int. Solid-State Circuit Conf. Dig., San Francisco, USA, 1996 pp. 392-393.
[145] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, Dec. 2002.
[146] Y. C. Chang, Y. C. Hsu, S. G. Lin, Y. Z. Juang, and H. K. Chiou, “On-wafer single contact quadrature accuracy measurement using receiver mode in four-port vector network analyzer,” IEEE MTT-S Int. Microwave Symp. Dig., 2008, pp. 371–374.
[147] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-m CMOS,”IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, Nov. 2004.
[148] B. M. Helal, C.-M. Hsu, K. Johnson, and M. H. Perrott, “A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1391-1400, May. 2009.
[149] I-T. Lee, Y.-J. Chen, S.-I. Liu, C.-P. Jou, F.-L. Hsueh, and H.-H. Hsieh, “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing ” IEEE Int. Solid-State Circuits Conf., Tech. Dig., Feb. 2013, pp. 414-415.
[150] Y.-C. Huang and S.-I. Liu, “A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing” IEEE Int. Solid-State Circuits Conf., Tech. Dig., Feb. 2012, pp. 338-341.
[151] B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008.
[152] F.-R. Liao and S.-S. Lu, "A programmable edge-combining DLL with a current-splitting charge pump for spur suppression,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 12, pp. 946-950, Dec. 2010.
[153] 詹駿清,毫米波注入鎖定振盪器及鎖頻迴路之研究,國立中央大學電機工程研究所碩士論文,民國104年。
[154] 黃書彥,鎖頻迴路及追蹤與保持放大器之研製,國立中央大學電機工程研究所碩士論文,民國104年。
[155] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed Milimeter-Wave Wireless Systems,” IEEE ICCSC 2008, pp. 812-815.
[156] A. Pottbacker, U. Langmann, and H.-U. Schreiber “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992.
[157] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009.
[158] D. B. Lesson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE., vol. 54, Feb. 1966, pp. 329-330.
[159] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp. 652–660, Mar. 2005.
[160] S. Yun, S. Shin, H. Choi, and S. Lee, “A 1 mW current-reuse CMOS differential LC-VCO with low phase noise,” Proc. IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 540–541.
[161] H. H. Hsieh and L. H. Lu, “A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations,” IEEE MTT-S Int. Microwave Symp. Digest, vol. 55, no. 3, pp. 467-473, Mar. 2007.
[162] H.-Y. Chang, Y.-L. Yeh, Y.-C. Liu, M.-H. Li, and K. Chen, “A low jitter low phase noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65 nm CMOS technology,” IEEE Trans. Microw. Theory & Techn., vol. 62, no. 03, pp. 543-555, Mar. 2014.
[163] S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “19.2 A PVT-robust −39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers, ” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 324-325.
[164] 李昇洺,V及D頻段高除頻數注入鎖定除頻器與四相位鎖頻迴路之研製,國立中央大學電機工程研究所碩士論文,民國106年。
[165] H. T. Bui et al., “Design of a high-speed differential frequency-to-voltage converter and its application in a 5 GHz frequency locked loop,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no.4, pp. 766–774, Apr. 2008.
[166] 沈毅恩,K頻段互補式金氧半場效電晶體低功耗低相位雜訊四相位時脈產生器之研製,國立中央大學電機工程研究所碩士論文,民國106年。
[167] “Optimization of quadrature modulator performance,” Technical Notes and Articles, RF Micro Devices Inc.
|