博碩士論文 105521107 詳細資訊




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姓名 劉浩恩(Hao-En Liu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 微波及毫米波切換器及四相位壓控振盪器整合除三 除頻器之研製
(Design of Microwave and Millimeter-Wave Switches and Quadrature Voltage-Controlled Oscillator Integrated a Divide-by-Three Frequency Divider)
相關論文
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★ 微波毫米波寬頻振盪器與鎖相迴路之研製★ 使用達靈頓對之單晶微波及毫米波寬頻電路
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摘要(中) 摘要
隨著無線通訊快速的發展,半導體製程發展成熟及高速資料傳輸量的需求,
許多系統已廣泛應用在微波與毫米波頻段上。在無線通訊系統中,高性能切換器
為射頻前端的一個重要區塊。 第一章本論文的緒論。 第二章介紹數個射頻切換器
及設計原理, 分別採用行進波、 分佈式及疊接式架構設計單刀單擲和單刀雙擲切
換器並使用由穩懋半導體所提供 0.15 μm 及 0.1 μm GaAs 製程, 其中單刀雙擲行
進波切換器量測頻寬為 DC 至 36.5 GHz, 插入損耗皆小於 3 dB, 在目標頻率為
38 GHz 時插入損耗為 3.1 dB, 隔離度為 39.34 dB; 而單刀雙擲疊接式切換器量
測, 頻寬為 23 至 49 GHz,插入損耗皆小於 2 dB,在目標頻率為 39.3 GHz 時插
入損耗為 1.47 dB,隔離度為 15.25 dB, 輸入 1 dB 增益壓縮點高於 20 dBm。
第三章藉由台積電 40 奈米 CMOS 製程,設計了 W 頻帶鎖相迴路之前端電
路,並訂定了中心頻率為 94 GHz 的設計目標, 實現次諧波注入鎖定四相位壓控
振盪器整合注入鎖定除三除頻器之試製。 振盪器量測的頻寬範圍為 93.28 到
97.37 GHz, 可調頻寬為 4.1 GHz,輸出功率高於-22.4 dBm,距載波偏移 1-MHz
的相位雜訊約為 -80 dBc/Hz, 而注入鎖定除頻器的輸出功率亦有在本章節量測
完畢。 此電路直流總功耗為 43 mW。
第四章為整合應用於 Ka 頻帶之中性化寬頻功率放大器及具鎖相迴路自對準
之次諧波注入鎖定壓控振盪器藉由台積電 90 奈米 CMOS 製程。量測的鎖頻範圍
為 32.78 到 34.85 GHz,各個控制電壓的鎖定範圍約為 55 MHz,輸出功率高於 -
11.62 dBm, 最低的距載波偏移 1-MHz 的相位雜訊為-106.3 dBc/Hz,抖動量積分
範圍由 1 kHz 到 40 MHz 為 179 fs。 整合注入鎖定鎖相迴路及功率放大器後的量
測鎖頻範圍為 32.8 到 34.8 GHz,輸出功率高於 1.73 dBm。 鎖相迴路直流總功耗
為 68.15 mW。
最後,第五章概括本論文所提出之研究成果,及可研究內容於毫米波前端收
發機切換器子電路及在直接轉換的收發機系統中高頻四相位壓控振盪器,在未來
的研究方向將集成射頻前端電路, 未來的成果有望滿足收發器的實際應用。
摘要(英) Abstract
With the rapid growth of wireless communication, the development of
semiconductor processes and the demand for high-speed data transmission, numerous
systems have been widely used in the microwave and millimeter-wave (MMW) bands.
In wireless communication systems, high-performance switches are an important block
in the radio frequency (RF) front end. Chapter 1 is the introduction of the thesis.
Chapter 2 introduces several RF switches and the design principles for single-pole
single-throw (SPST) and single-pole double-throw (SPDT) switches with travelingwave, distributed-type and stacked-FETs architectures. The switches are implemented
using 0.15 μm and 0.1 μm GaAs processes provided by WIN Semiconductors. The
SPDT traveling-wave switch has a measured bandwidth from DC to 36.5 GHz, an
insertion loss of less than 3 dB, an insertion loss of 3.1 dB at a target frequency of 38
GHz, and an isolation of 39.34 dB. The stacked-FETs SPDT switch has a measured
bandwidth from 23 to 49 GHz with an insertion loss of less than 2 dB and an insertion
loss of 1.47 dB and an isolation of 15.25 dB at a target frequency of 39.3 GHz. The
measured insertion loss degrades 1 dB (P1dB) is higher than 20 dBm.
Chapter 3, a W-band phase-locked loop front-end is designed using the TSMC
40nm CMOS process, and the center frequency is 94 GHz. A sub-harmonically
injection-locked quadrature voltage-controlled oscillator (QVCO) is integrated with an
injection-locked divide-by-three frequency divider. The QVCO has a measured
bandwidth from 93.28 to 97.37 GHz with a tuning range of 4.1 GHz, an output power
of higher than -22.4 dBm, and a phase noise at 1-MHz offset of -80 dBc/Hz. In addition,
the measured output powers of the injection-locked frequency divider also presented in
this chapter. The total DC power consumption of the circuit is 43 mW.
Chapter 4, a Ka-band integration of a neutralized wideband power amplifier (PA)
and a sub-harmonically injection-locked phase-locked loop (SILPLL) is implemented
using the TSMC 90 nm CMOS process. The measured SILPLL locking range is from
32.78 to 34.85 GHz, the locking range of each control voltage is about 55 MHz, the
output power is higher than -11.62 dBm, and the minimum phase noise at 1-MHz offset
is -106.3 dBc/Hz. The root mean square (RMS) jitter integrated from 1 kHz to 40 MHz
is 179 fs. The integrated SILPLL and PA chip has a measured locking range from 32.8
to 34.8 GHz and an output power of higher than 1.73 dBm. The total DC power
consumption of the circuit is 68.15 mW.X
Finally, Chapter 5 summarizes the research results presented in this thesis, and the
future works: sub-circuit in the millimeter-wave front-end transceiver switch and high
frequency quadrature voltage-controlled oscillator in the direct conversion transceiver
system. The research direction will be integrated RF front-end circuits, and the future
results are expected to meet the practical application of the transceiver.
關鍵字(中) ★ 砷化鎵
★ 互補式金屬氧化物半導體
★ 切換器
★ 壓控振盪器
★ 注入鎖定除頻器
★ 次諧波注入鎖相迴路
關鍵字(英) ★ GaAs
★ CMOS
★ Switch
★ VCO
★ ILFD
★ SILPLL
論文目次 Content
Abstract.....................................................................................IX
摘要............................................................................................XI
誌謝..........................................................................................XII
List of Figures........................................................................XVI
List of Tables ....................................................................... XXII
Chapter 1 .................................................................................... 1
Introduction................................................................................ 1
1.1 Motivation ................................................................................................................... 1
1.2 Literature Survey ....................................................................................................... 3
1.3 Contributions.............................................................................................................. 5
1.4 Theory Organization.................................................................................................. 5
Chapter 2 .................................................................................... 7
Microwave and Millimeter-Wave MMIC Switches in
0.15 μm and 0.1 μm GaAs pHEMT Processes ........................ 7
2.1 Introduction ................................................................................................................ 7
2.1.1 Millimeter-Wave Communication System............................................................ 9
2.1.2 Basic Concepts of Switch.................................................................................... 10
2.2 Processes Introduction ............................................................................................. 10
2.2.1 0.15 μm GaAs pHEMT Process .......................................................................... 10
2.2.2 0.1 μm GaAs pHEMT Process ............................................................................ 11
2.3 38 GHz MMIC Traveling-Wave Switches Using 0.15 μm GaAs pHEMT Process
Implementation.................................................................................................................. 11
2.3.1 38 GHz MMIC SPST and SPDT Traveling-Wave Switches .............................. 12
2.3.2 38 GHz MMIC SPST and SPDT Traveling-Wave Switches Measurement Results
......................................................................................................................................... 25
2.4 39.3 GHz MMIC Switches Using 0.1 μm GaAs pHEMT Process Implementation
............................................................................................................................................. 32
2.4.1 39.3 GHz MMIC SPST Distributed-Type Switch............................................... 34
2.4.2 39.3 GHz MMIC SPDT Stacked-FETs Switch................................................... 38
2.4.3 39.3 GHz MMIC SPST and SPDT Switches Measurement Results ................... 51
2.5 Performance Summary............................................................................................ 61
Table 2-10. Performance Summary of the 38 GHz and 39.3 GHz Switches ...................... 63XIV
Chapter 3 .................................................................................. 64
A W-band 40 nm CMOS Sub-harmonically InjectionLocked Quadrature Voltage-Controlled Oscillator
Integrated Injection-Locked Divide-by-Three Frequency
Divider....................................................................................... 64
3.1 Introduction .............................................................................................................. 64
3.1.1 TSMC 40 nm CMOS Process Introduction......................................................... 66
3.1.2 Motivation of W-Band Communication System.................................................. 66
3.2 Circuit Implementation............................................................................................ 68
3.2.1 Quadrature Voltage-Controlled Oscillator .......................................................... 69
3.2.2 Injection-Locked Frequency Divider (ILFD) ...................................................... 75
3.2.3 Pulse Generator (PG)........................................................................................... 80
3.3 Sub-harmonically Injection-Locked Quadrature Voltage-Controlled Oscillator
Integrated Injection-Locked Divide-by-Three Frequency Divider Measurement
Results................................................................................................................................. 88
3.4 Performance Summary and Future Work for W-band system............................ 99
Table 3-6. Performance Summary of the Work for W-band System................................. 101
Chapter 4 ................................................................................102
Integration Ka-Band Application of a Neutralized Wideband
Power Amplifier and Sub-harmonically Injection-Locked
VCO with Phase-Locked Loop Self-Alignment Technique
..................................................................................................102
4.1 Introduction ............................................................................................................ 102
4.1.1 Millimeter-Wave K-Band Communication System........................................... 103
4.1.2 Process Introduction .......................................................................................... 104
4.2 PLL Circuit Implementation................................................................................. 105
4.2.1 Sub-harmonically Injection-Locked QVCO...................................................... 106
4.2.2 Injection-Locked Frequency Divider................................................................. 107
4.2.3 Current Mode Logic (CML) Divider................................................................. 108
4.2.4 Phase Detector................................................................................................... 109
4.2.5 Frequency Detector ........................................................................................... 109
4.2.6 Pulse Generator ................................................................................................. 110
4.3 Power Amplifier Circuit Implementation ............................................................ 111
4.4 Measurement Results ............................................................................................. 112
4.4.1 Power Amplifier Measurement Result .............................................................. 112
4.4.2 PLL Measurement Result .................................................................................. 117XV
4.5 Performance Summary and Future Work........................................................... 140
Table 4-2. Performance Summary of the Sub-harmonic Injection-Locked Oscillator with
Self-Alignment Technique of Phase-Locked Loops ......................................................... 142
Chapter 5 ................................................................................143
Conclusions and Future Works............................................143
Reference ................................................................................145
Publish.....................................................................................153
參考文獻 Reference
Binqi Yang, Zhiqiang Yu, Ji Lan, Ruoqiao Zhang, Jianyi Zhou, and Wei Hong,
“Digital Beamforming-Based Massive MIMO Transceiver for 5G MillimeterWave Communications,” in IEEE Trans. Microw. Theory Tech., vol. 66, no. 07,
pp. 3403-3418, July. 2018.
H. Takasu, F. Sasaki, H. Kawasaki, H. Tokuda, and S. Kamihashi, “W-band SPST
transistor switches,” IEEE Microw. Guided Wave Lett., vol. 6, no. 12,pp. 315-316,
Sept. 1996.
D. L. Ingram, K. Cha, K. Hubbard, and R. Lai, “Q-band high isolation GaAs
HEMT switches,” in IEEE GaAs Integr. Circuits Symp. Dig., Orlando, FL, Nov.
1996, pp. 282-289.
D. C. W. Lo, H. Wang, B. R. Allen, G. S. Dow, K. W. Chang, M. Biedenbender,
R. Lai, S. Chen, and D. Yang, “Novel monolithic multifunctional balanced
switching low-noise amplifiers,” IEEE Trans. Microw. Theory Tech., pt. 2, vol.
42, pp. 2629-2634, Dec. 1994.
K. Y. Lin, Y. J. Wang, D. C. Niu, and H. Wang, “Millimeter-wave MMIC singlepole–double-throw passive HEMT switches using impedance transformation
networks,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 4, pp. 1076-1085, Apr.
2003.
M. J. Schindler and A. Morris, “DC-40 GHz and 20-40 GHz MMIC SPDT
switches,” IEEE Trans. Microw. Theory Tech., vol. 87, no. 1, pp. 1486-1493, Dec.
1987.
T. Shimura, Y. Mimino, and K. Nakamura, “High isolation V -band SPDT switch
MMIC for high power use,” in IEEE MTT-S Int. Microw. Symp. Dig., vol. 1, May
2001, pp. 245-248.
H. Mizutani, N. Funabashi, M. Kuzubara, and Y. Takayama, “Compact DC-60-
GHz HJFET MMIC switches using ohmic electrode-sharing technology,” IEEE
Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1597-1603, Nov. 1998.
H. Mizutani and Y. Takayama, “DC-110-GHz MMIC traveling-wave switch,”
IEEE Trans. Microw. Theory Tech., vol. 48, no. 5, pp. 840-845, May 2000.
P. Bermkopf, M. Schindler, and A. Bertrand, “A high power K/Ka-band
monolithic T/R switch,” IEEE Microw.and Millimeter-Wave Monolithic Circuits
Symp. Dig., June 1991, pp. 15-18.
Kun-You Lin, Wen-Hua Tu, Ping-Yu Chen, Hong-Yeh Chang, Huei Wang, and
Ruey-Beei Wu, “Millimeter-Wave MMIC Passive HEMT Switches Using
Traveling-Wave Concept,” in IEEE Trans. Microw. Theory Tech., vol. 52, no. 8,
Aug. 2004, pp. 1798-1808.146
R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and
B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard
0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872,
Nov. 2004.
D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang. F. Wang, and M.-C.
F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a
heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp.
1606-1617, Jul. 2011.
Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, and M.-C F. Chang, “A 70-78 integrated
CMOS frequency synthesizer for W-band satellite communications,” IEEE Trans.
Microw. Theory Tech., vol. 59, no. 12, pp. 3206-3218, Dec. 2011.
H.-K. Chen, T. Wang, and S.-S. Lu, “A millimeter-wave CMOS triple-band phaselocked loop With A Multimode LC-Based ILFD,” IEEE Trans. Microw. Theory
Tech., vol. 59, no. 5, pp. 1327-1338, May 2011.
S. Shahramian, A. Hart, A. Tomkins, A. C. Carusone, P. Garcia, P. Chevalier, and
S. P. Voinigescu, “Design of a dual W- and D-band PLL,” IEEE J. Solid-State
Circuits, vol. 46, no. 5, pp. 1011-1022, May 2011.
K.-H. Tsai and S.-I. Liu, “A 104-GHz phase-locked loop using a VCO at second
pole frequency,” IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, pp.
80-88, Jan. 2012.
C.-C. Wang, Z. Chen, and P. Heydari, “W-Band silicon-based frequency
synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw.
Theory Tech., vol. 60, no. 5, pp. 1307-1320, May 2012.
L. Ye, Y. Wang, C. Shi, H. Liao, and R. Huang, “A W-band divider-less cascading
frequency synthesizer with push-push ×4 frequency multiplier and sampling PLL
in 65nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., pp.1-3, Jun. 2012.
A. Tang, D. Murphy, G. Virbila, F. Hsiao, S.-W. Tam, H.-T. Yu, H.-H. Hsieh, C.-
P. Jou, Y. Kim, A. Wong, A. Wong, Y.-C. Wu, and M.-C. F. Chang, “D-band
frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS
technology,” in IEEE MTT-S Int. Microw. Symp. Dig., pp.1-3, Jun. 2012.
G. Liu, A. Trasser, and H. Schumacher, “A 64-84-GHz PLL with low phase noise
in an 80-GHz SiGe HBT technology,” IEEE Trans. Microw. Theory Tech., vol.
60, no. 12, pp. 3739-3748, Dec. 2012.
劉深淵、楊清淵, 鎖相迴路, 滄海書局, 民國 100 年.
Toshiyuki Inoue, Kensuke Ikeda, Yasuyuki Kakubari, Naruto Yonemoto,
Nobuhiko Shibagaki, Hiroyuki Toda, and Hiroshi Murata, “Millimeter-Wave
Wireless Signal Generation and Detection Using Photonic Technique for Mobile147
Communication Systems,” IEEE International Topical Meeting on Microw.
Photonics (MWP), Nov. 2016, pp. 55-58.
Wei Hong, Jianyi Zhou, et al., “Research advances in microwave and millimeter
wave circuits and systems in the SKLMMW,” in 2012 19th International Conf. on
Microw. Radar & Wireless Communications, May. 2012, pp. 807-809.
S. F. Chang, and W.-L. Chen, J.-L. Chen, H.-W. Kung, and, H.-Z. Hsu, “New
millimeter-wave MMIC switch design using the image-filter synthesis method”,
in IEEE Microw. and Wireless Component Lett., vol. 14, no. 3, pp. 103-105, March
2004.
J. Kim, W. Ko, S.-H. Kim, J. Jeong, and Y. Kwon, “A High Performance 40-85
GHz MMICSPDT Switch Using FET Integrated Transmission Line Structure,” in
IEEE Microw. and Wireless Component Lett., vol. 13, no. 12, pp. 505-507, Dec.
2003.
Zuo-Min Tsai, Mei-Chao Yeh, Ming-Fong Lei, Hong-Yeh Chang, Chin-Shen Lin,
and, Huei Wang, “DC-to-135 GHz SPST and 15-to-135 GHz SPDT Traveling
Wave Switches Using FET-Integrated CPW Line Structure,” in IEEE MTT-S
International Microw. Symp. Dig., June. 2005, pp. 1393-1396.
詹清硯, “微波及毫米波行進波切換器之研製,” 國立中央大學電機工程研究
所碩士論文, 民國 98 年 6 月.
Sonnet User’s Manual, Sonnet Software Inc., Liverpool, NY,1998.
Saqib Kaleem, Jutta Kuhn, Rudiger Quay, and Matthias Hein, “A High-Power Kaband Single-pole Single-throw Switch MMIC using 0.25 µm GaN on SiC,” 2015
IEEE Radio and Wireless Symp. (RWS), June. 2015, pp. 132-134.
W.E. Doherty and R.D. Joos, “The PIN-diode circuit designers’ handbook,”
Microsemi Corporations, pp. 3-8, 1998.
M. Hangai, T. Nishino, Y. Kamo, and M. Miyazaki, “An S-band 100W GaN
protection switch,” IEEE MTT-S International Microw. Symp., June 2007, pp.
1389-1392.
Hong-Yeh Chang and Ching-Yan Chan, “A Low Loss High Isolation DC-60 GHz
SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS
Process,” IEEE Microw. and Wireless Components Lett., vol. 20, no. 2, 2010, pp.
82-84.
Microwave Engineering David M Pozar. 4ed Wiley 2012.
A. Colquhoun and L. P. Schmidt, “MMICs for automotive and traffic applications,”
GaAs IC Symp. Tech. Dig. 1992, Miami Beach, FL, USA, 1992, pp. 3-6.
Wei Hongtao, Gao Xuebang, Wu Hongjiang, Wei Bihua and, Lu Yanan, “W-band
GaAs PIN Diode SPST Switch MMIC,” 2012 International Conf. on
Computational Problem-Solving (ICCP), Leshan, 2012, pp. 93-95.148
Wenju Li, Kaixue Ma and, Shouxian Mou, “A Ku-band High-Isolation SPDT
Switch in 0.35μm SiGe BiCMOS Technology,” 2016 International Symp. on
Integr. Circuits (ISIC), Singapore, 2016, pp. 1-4.
M. Davulcu, E. Ö zeren, M. Kaynak and, Y. Gurbuz, “A New 5-13 GHz SlowWave SPDT Switch With Reverse-Saturated SiGe HBTs,” in IEEE Microw. and
Wireless Components Lett., vol. 27, no. 6, pp. 581-583, June 2017.
M. Hieda, K. Nakahara, K. Miyaguchi, H. Kurusu, Y. Iyama, T. Takagi and, S.
Urasaki, “High-Isolation Series-Shunt FET SPDT Switch With a Capacitor
Canceling FET Parasitic Inductance,” IEEE Trans. on Microw. Theory and Tech.,
vol. 49, no. 12, pp. 2453-2458, Dec. 2001.
M. Uzunkol and G. Rebeiz, “A Low-Loss 50-70 GHz SPDT Switch in 90 nm
CMOS,” in IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 2003-2007, Oct. 2010.
R. Shu, A. Tang, B. Drouin, and Q. J. Gu, “A 54-84 GHz CMOS SPST Switch
with 35 dB Isolation,” 2015 IEEE Radio Frequency Integr. Circuits Symp. (RFIC),
Phoenix, AZ, 2015, pp. 15-18.
Dongning Hao, Nan Li, and Xiuping Li, “A Split-Ring Resonator (SRR) based
Millimeter-Wave SPST Switch in 0.13µm BiCMOS Technology,” 2016 IEEE
International Conf. on Computational Electromagnetics (ICCEM), Guangzhou,
2016, pp. 236-238.
M. Thian and V. Fusco, “40-70 GHz 13 Gbps 1-dB Loss SPST and SPDT
Differential Switches in 0.35 μm SiGe Technology,” Active RF Devices, Circuits
and Systems Seminar, Belfast, 2011, pp. 11-15.
L. Zhao, W. F. Liang, J. Y. Zhou, and X. Jiang, “Compact 35-70 GHz SPDT
Switch With High Isolation for High Power Application,” in IEEE Microw. and
Wireless Components Lett., vol. 27, no. 5, pp. 485-487, May 2017.
H. Jia, B. Chi, L. Kuang, and Z. Wang, “A bidirectional short range low power
and high data rate W-Band transceiver for network on chip,” 2018 16th IEEE
International New Circuits and Systems Conf. (NEWCAS), 2018, pp. 87-90.
A. Shokrollahi et al., “10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded
clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS,”
2016 IEEE ISSCC., San Francisco, CA, pp. 182-183, 2016.
H. J. Lee, J. G. Lee, C. J. Lee, T. H. Jang, H. J. Kim, and C. S. Park, “High-speed
and low-power OOK CMOS transmitter and receiver for wireless chip-to-chip
communication,” 2015 IEEE MTT-S International Microw. Workshop Series on
Advanced Materials and Processes for RF and THz Applications (IMWS-AMP),
Suzhou, 2015, pp. 1-3.
Malte Giese, Christian Friesicke, and Arne F. Jacob, “Concept and system analysis
of wideband transmit front-ends for high data rate communication systems at W149
band,” in 2014 20th International Conference on Microw. Radar and Wireless
Communications (MIKON), 2014, pp. 1-4.
Xinying Li, Ze Dong, Jianjun Yu, Junwen Zhang, Li Tao, Yufeng Shao, and Nan
Chi, “Performance Improvement by Pre-equalization in W-band RoF System,” in
2013 Optical Fiber Communication Conf. and Exposition and the National Fiber
Optic Engineers Conf. (OFC/NFOEC), 2013, pp. 1-3.
Zhihua Zhou, Jing He, Rui Deng, QingHui Chen, and Lin Chen, “A DCT-spread
FOFDM Signal with Low PAPR in W-band RoF System,” 2017 International
Topical Meeting on Microw. Photonics (MWP), 2017, pp. 1-4.
D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C.
F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a
heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7,
pp.1606-1617, Jul. 2011.
V. Jain, B. Javid, and P. Heydari, “A BiCMOS dual-band millimeter-wave
frequency synthesizer for automotive radars,” IEEE J. Solid-State Circuits, vol.
44, no. 8, pp. 2100-2113, Aug. 2009.
A. Arbabian, S. Kang, S. Callender, J.-C. Chien, B. Afshar, and A.Niknejad, “A
94 GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition,”
IEEE Int. Symp. on VLSI Design, Automation and Test, Jun. 2012, pp. 56-57.
T. Y. Chang, C. S. Wang, and C. K. Wang, “A low power W-band PLL with 17-
mW in 65-nm CMOS technology,” IEEE Asian Solid-State Circuits Conf. Tech.
Dig., Nov. 2012, pp. 81-84.
S. Kang, J. C. Chien, and A. M. Niknejad, “A W-Band Low-Noise PLL With a
Fundamental VCO in SiGe for Millimeter-Wave Applications,” in IEEE Trans. on
Microw. Theory and Tech., vol. 62, no. 10, pp. 2390-2404, Oct. 2014.
X. Yi, Z. Liang, G. Feng, C. C. Boon, and F. Meng, “A 93.4-to-104.8 GHz 57 mW
fractional-N cascaded sub-sampling PLL with true in-phase injection-coupled
QVCO in 65 nm CMOS,” 2016 IEEE Radio Frequency Integr. Circuits Symp.
(RFIC), San Francisco, CA, 2016, pp. 122-125.
K. H. Tsai and S. I. Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” 2009 IEEE
International Solid-State Circuits Conf. Dig. Papers, San Francisco, CA, 2009, pp.
276-277.
J. Lee, M. Liu, and H. Wang, “A 75-GHz phase-locked loop in 90-nm CMOS
technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008.
S. Kang, J.-C. Chien, and A. M. Niknejad, “A 100GHz phase-locked loop in
0.13µm SiGe BiCMOS process,” in Proc. IEEE Radio Freq. Integr. Circuits
Symp., pp.1-4, Jun. 2011.150
Z. Chen, C. C. Wang, and P. Heydari, “W-band frequency synthesis using a Kaband PLL and two different frequency triplers,” 2011 IEEE Radio Frequency
Integr. Circuits Symp., Baltimore, MD, 2011, pp. 1-4.
K. W. Tan, T. S. Chu, and S. S. H. Hsu, “A 76.2–89.1 GHz Phase-Locked Loop
With 15.6% Tuning Range in 90 nm CMOS for W-Band Applications,” in IEEE
Microw. and Wireless Components Lett., vol. 25, no. 8, pp. 538-540, Aug. 2015.
S. Shahramian, A. Hart, A. Tomkins, A. C. Carusone, P. Garcia, P. Chevalier, and
S. P. Voinigescu, “Design of a dual W- and D-band PLL,” IEEE J. Solid-State
Circuits, vol. 46, no. 5, pp. 1011-1022, May 2011.
L. Ye, Y. Wang, C. Shi, H. Liao, and R. Huang, “A W-band divider-less cascading
frequency synthesizer with push-push ×4 frequency multiplier and sampling PLL
in 65nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp.1-3.
G. Liu, A. Trasser, and H. Schumacher, “A 64–84-GHz PLL with low phase noise
in an 80-GHz SiGe HBT technology,” IEEE Trans. Microw. Theory Tech., vol.
60, no. 12, pp. 3739-3748, Dec. 2012.
A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, “A
low phase noise quadrature injection locked frequency synthesizer for mm-wave
applications,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp.2635-2649, Nov.
2011.
詹駿清, “毫米波注入鎖定振盪器及鎖頻迴路之研究,” 國立中央大學電機工
程研究所碩士論文, 民國 105 年.
Yin-Cheng Chang, Yin-Chung Chiu, Shuw-Guann Lin, Ying-Zong Juang, and
Hwann-Kaeo Chiou, “High Phase Accuracy On-Wafer Measurement for
Quadrature Voltage-Controlled Oscillator,” 37th European Microw. Conf.,
Munich, Germany, Oct. 2007, pp. 340–343.
李昇洺, “V 及 D 頻段高除頻數注入鎖定除頻器與四相位鎖頻迴路之研製,”
國立中央大學電機工程研究所碩士論文, 民國 106 年 6 月.
葉瀚濃, “用注入鎖定技術之 W 頻段除三除頻器與 V 頻段除六除頻器及 Q
頻段鎖頻迴路,” 國立中央大學電機工程研究所碩士論文, 民國 107 年.
Y.-L. Yeh and H.-Y. Chang, “Design and analysis of a W-band divide-by-three
injection-locked frequency divider using second harmonic enhancement
technique,” IEEE Trans. Microw. Theory. Tech., vol. 60, no. 6, pp.1617-1625, Jun.
2012.
邱煥凱, 毫米波主被動目標偵測關鍵前端積體電路研製, 科技部專題研究計
畫書, 民國 106 年.
T. Tokumitsu, “K-band and millimeter-wave MMICs for emerging commercial
wireless applications,” IEEE Trans. Microw. Theory & Tech., vol. 49, no. 11, pp.
2066-2072, Nov. 2001.151
Zhen-Yu Zhang, Ying Rao Wei, and Ke Wu, “Millimeter-Wave Wireless
Communication Systems Integrated with a Novel Receiver Front-End,” in IEEE
MTT-S International Microw. Symp., 2010, pp.1612-1615.
Saverio Alessandro, Maria Concetta De Bilio, Ignazio Pomona, Salvatore
Coco, Gaspare Bavetta, and Antonio Laudani, “Analog Beamforming Network
for Ka Band Satellite on the Move Terminal with phase shifting technique based
on I/Q mixer,” in 2015 European Radar Conf. (EuRAD), 2015, pp.445-448.
Filipe Tabarani, Luigi Boccia, Tatyana Purtova, Alireza Shamsafar, Hermann
Schumacher, and Giandomenico Amendola,“ 0.25-µm BiCMOS System-onChip for K-/Ka-Band Satellite Communication Transmit-Receive Active Phased
Arrays,” in IEEE Trans. on Microw. Theory and Tech., vol. 66, no. 5, May, 2018.
Fang Zhu, Zhe Chen, Jixin Chen, Wei Hong, and Ke Wu, “A Ka-band Transceiver
Front-end Module for Wide Band Wireless Communication,” in 2011
International Conf. on Computational Problem-Solving (ICCP), 2011, pp.719-722.
B.-W. Min and G. M. Rebeiz, “Single-ended and differential Ka-band BiCMOS
phased array front-ends,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2239-
2250, Oct. 2008.
C. Liu et al, “A Ka-band single-chip SiGe BiCMOS phased-array transmit/receive
front-end,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 11, pp. 3667-3677,
Nov. 2016.
賴俐妏,“應用於 X/Ka 頻段之互補式金氧半導體寬頻中性化功率放大器暨
應用低阻抗二元功率結合技術與多蒂架構於 X 頻帶氮化鎵功率放大器之
研製,” 國立中央大學電機工程研究所碩士論文, 民國 107 年 7 月.
T.-N. Luo, S.-Y. Bai, and Y.-J. E. Chen, “A 60-GHz 0.13 µm CMOS divide-bythree frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp.
2409-2415, Nov. 2008.
B.-Y. Lin and S.-I. Liu, “Analysis and design of D-band injection-locked
frequency dividers,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1250-1264,
Jun. 2011.
A. Musa, K. Okada, and A. Matsuzawa, “Progressive mixing technique to widen
the locking range of high division-ratio injection-locked frequency dividers,”
IEEE Trans. Microw. Theory Tech., vol. 61, no. 3, pp. 1161-1173, Mar. 2013.
D. Shin and K. J. Koh, “An Injection Frequency-Locked Loop—Autonomous
Injection Frequency Tracking Loop With Phase Noise Self-Calibration for PowerEfficient mm-Wave Signal Sources,” in IEEE J. Solid-State Circuits, vol. 53, no.
3, pp. 825-838, March 2018.152
K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66GHz
quadrature PLL in 45nm digital CMOS,” in IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 2009, pp. 494-495.
W. EI-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, and M. Hossain,
“A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers
with less than 100-fs jitter based on cascaded PLL architecture,” IEEE Trans.
Microw. Theory & Tech., vol. 65, no. 2, pp. 396-413, Feb. 2017.
X. Yi, C.C. Boon, H. Liu, J. F. Lin, and W. M. Lim, “A 57.9-to-68.3GHz 24.6
mW frequency synthesizer with in-phase injection-coupled QVCO in 65-nm
CMOS technology,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 347-359, Feb.
2014.
A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, “A
low phase noise quadrature injection locked frequency synthesizer for mm-wave
applications,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2635-2649, Nov.
2011.
W. Deng, T. Siriburanon, A. Musa, K. Okada, and A. Matsuzawa, “A subharmonic injection-locked quadrature frequency synthesizer with frequency
calibration scheme for millimeter-wave TDD transceivers,” IEEE J. Solid-State
Circuits, vol. 48, no. 7, pp. 1710-1720, July 2016.
T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada,
and A. Matsuzawa, “A low-power low-noise mm-wave subsampling PLL using
dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for
IEEE 802.11ad,” IEEE J. Solid-State Circuits, vol. 51, no. 5, pp. 1246-1260, May
2016.
H.-Y. Chang, C.-C. Chan, I.-Y. Shen, Y.-L. Yeh, and S.-Y. Huang, “Design and
analysis of CMOS low-phase-noise low-jitter sub-harmonically injection-locked
VCO with FLL self-alignment technique,” IEEE Trans. Microw. Theory & Tech.,
vol. 64, no. 12, pp. 4632-4645, Dec. 2016.
指導教授 張鴻埜(Hong-Yeh Chang) 審核日期 2019-8-19
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