以90-nm CMOS 製程實現之47-GHz 壓控振盪器設計

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姓名

黃才源(Tsai-Yuan Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以90-nm CMOS 製程實現之47-GHz 壓控振盪器設計
(A 47-GHz Voltage Controlled Oscillator in 90-nm CMOS Process)

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摘要(中)

本篇論文提出一個可應用於毫米波通訊的47-GHz的壓控振盪器，採用90-nm CMOS製程實現，擁有低成本且體積小的優點。此電路使用交互耦合對的電晶體產生負電阻，使其能夠在高頻中更容易維持振盪條件，並透過緩衝器及電壓放大器輸出，使輸出功率可提高至2.7 dBm。在操作電壓1.2 V下，整體電路的功耗為49.65 mW。為了增加振盪器的可調頻寬，本文提出於振盪器電路中加入8組的可開關電容器，使振盪器可藉由切換電容達到增加調頻範圍的效果，當操作於47-GHz時的單一可調頻寬為3.16%，而總可調頻寬則可達到10.38 %。此電路在post-simulation時其在雜訊頻率1 MHz的結果為-86.82 dBc/Hz。
為了提供壓控振盪器所需的8個數位控制位元，並且避免因為加入的pad數量太多而使晶片面積增加，本文提出一種低延遲、低功耗的3-Wire數位控制電路加入於壓控振盪器的電路前端，藉由SPI的通訊介面將一串數位訊號提供給3-wire電路，將訊號中的8個數位控制位元儲存於移位暫存器之後，利用並接的暫存器從接收的數位訊號中擷取出所需的8個控制位元給予壓控振盪器，此時僅需要3個輸入接腳(Clk (Clock), LE(Parallel-out Enable), D_in(Digital Data))，即可產生振盪器所需之8個數位控制位元，因此可以有效的縮減輸入數位控制位元所需的pad，而大幅減少晶片面積。

摘要(英)

In this thesis, a low-cost and compact 47-GHz voltage-controlled oscillator in a 90-nm CMOS technology for millimeter-wave communication is proposed. This circuit uses the cross-coupled transistors to generate a negative resistance that makes it easier to maintain oscillation conditions at high frequencies. The VCO increase the output power to 2.7 dBm with a buffer and a voltage amplifier. The power consumption is 49.65 mW from a 1.2 V supply. In order to increase the tuning range of the oscillator, this thesis proposes to add 8 sets of switchable capacitors to the oscillator circuit, so that it can increase the tuning range of the VCO by switching the capacitors. While the oscillator is operated at 47-GHz, the single tuning range is 3.16%, and the total tuning range is 10.38%. The phase noise at 1 MHz offset from the carrier is -86.82 dBc/Hz in post-simulation.
In order to provide the eight digital control bits to switch the capacitors of the VCO, and to avoid adding too much pads in this chip result in increasing the chip size, this thesis propose a low-delay and low-cost 3-wire digital control circuit that added to the VCO front end. A series of digital signals are provided to the 3-wire circuit through the communication interface of the SPI, and the digital control bits in the signal are stored in the shift register. Then, using the parallel register, the required eight control bits are extracted from the received digital signal to the VCO. At this time, only three input pins (Clk (Clock), LE(Parallel-out Enable), D_in(Digital Data)) are needed in this chip to generate the digital control bits required by the oscillator so that the pads for inputting the digital control bits can be effectively reduced, and the chip size will be greatly reduced.

關鍵字(中)

★ 壓控震盪器
★ 可變電容器
★ 數位控制

關鍵字(英)

★ VCO
★ Varactor
★ Digital Control

論文目次

摘要 I
Abstract II
致謝 III
目錄 V
圖目錄 VII
表目錄 XI
第一章緒論 1
1.1 振盪器及毫米波通訊應用 1
1.2 壓控振盪器架構比較 2
1.3 研究動機 9
1.4 論文架構 11
第二章壓控振盪器設計原理 12
2.1 原理分析 12
2.2 架構分析 13
2.3 可變電容器架構及原理分析 17
第三章可數位調控之47-GHz壓控振盪器設計電路介紹 28
3.1 壓控振盪器(Voltage Controlled Oscillator) 29
3.1.1 電路設計與分析 30
3.1.2 設計與佈局考量 36
3.1.3 模擬結果與討論 45
3.2 緩衝器與電壓放大器 48
3.2.1 設計與佈局考量 49
3.2.2 模擬結果與討論 53
3.3 3-Wire電路 58
3.3.1 電路分析與原理 61
3.3.2 設計與佈局考量 66
3.3.3 電路驗證與模擬結果 75
第四章總結與未來發展 83
4.1 總結 83
4.2 未來發展 84
參考文獻 85

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指導教授

傅家相李俊興(Jia-Shiang Fu Chun-Hsing Li)

審核日期

2019-7-23

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