使用鐵電可變電容與砷化鎵基晶片上電感之磁耦合全通相位偏移器

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姓名

吳可凡(Ke-Fan Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用鐵電可變電容與砷化鎵基晶片上電感之磁耦合全通相位偏移器
(A Magnetically Coupled All-Pass Phase Shifter Using Ferroelectric Varactors and GaAs-based On-Chip Inductors)

相關論文

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摘要(中)

相位偏移器是相位陣列中關鍵的電路之一，其功能為提供可調的植入相位。在相位陣列應用中，相移器通常須可達360°的相移量。若可提高單級相移器之相移量，則可減少串接的級數，期能降低植入損耗與電路面積。本篇論文採用具磁耦合的全通網路來設計一操作於2.4 GHz類比式相移器，設計目標為單級網路便可達到180°相移量。
我們以本實驗室所開發的基於鈦酸鍶鋇薄膜的鐵電可變電容技術，並與穩懋半導體提供之積體被動元件製程（WIPD）以覆晶鍵合方式整合，來實現此磁耦合全通相位偏移器。磁耦合全通網路中的耦合電感是以WIPD製程實現於GaAs基板上。我們設計兩電感互繞的極性使其對應的耦合係數為正值，以提升相位偏移量。模擬結果顯示，於2.45 GHz下，耦合係數可達0.8；若可變電容之可調度可達2.3，則相移量可達191°。
相移器中的鐵電可變電容製作於藍寶石基板上；可變電容量測結果顯示，於10 V偏壓下，電容可調度可達到約2.3。我們把以WIPD製程製作的GaAs晶片覆晶鍵合於藍寶石載板上，以組裝完成所設計之相移器。量測結果顯示，於10 V偏壓下，在2.35 GHz達到161°最大相移量，返回損耗皆大於11.3 dB，植入損耗皆小於15.8 dB
由同載板上的測試電容量測結果可知鐵電可變電容之品質因子較模擬預期差，導致了較高的植入損耗。另外，我們推測，因為覆晶鍵合的溫度較高，導致鐵電薄膜特性改變，造成可調度下降，以致相移量未如預期可超過180°。不過量測得之相移量亦已達161°，成功驗證以磁耦合全通網路架構來可實現高相移量之相位偏移器。

摘要(英)

Phase shifter is an essential component in a phased array. The function of a phase shifter is to provide a tunable insertion phase. In phased array applications, phase shift up to 360° is usually necessary. If the amount of phase shift provided by a single stage of phase shifter can be increased, the number of cascaded stages can then be reduced, which may lead to the reduction of insertion loss and circuit area. In this thesis, a 2.4-GHz analog phase shifter is designed at 2.4 GHz based on magnetically coupled all-pass network (MCAPN). The design goal is to achieve a phase shift up to 180° using only a single-stage network.
In this work, we use the ferroelectric varactor technology based on BSTO thin film developed by our lab and combine it with the integrated passive process offered by WIN Semiconductors (the WIPD process) by flip-chip bonding to realize the proposed magnetically coupled all-ass phase shifter. The coupled inductors in the MCAPN are realized using the WIPD process on a GaAs substrate. The polarity of the two intertwined inductors is designed to produce a positive coupling coefficient, which helps increase the amount of phase shift. Simulation results show that, at 2.45 GHz, a coupling coefficient of 0.8 can be achieved. If the tunability of the varactors is 2.3, the simulated phase shift is as high as 191°.
The ferroelectric varactors in the phase shifter are fabricated on a sapphire substrate. Measurement results of the varactors show that tunability of 2.3 is achieved under 10-V bias. The construction of the phase shifter is finalized by flip-chip mounting the GaAs chip onto the sapphire carrier. Measurement results of the phase shifter show that, under 10-V bias, maximum phase shift of 161° occurs at 2.35 GHz, with return loss greater than 11.3 dB and insertion loss less than 15.8 dB.
From the measurement results of the test varactors on the same carrier, it is found that the quality factor of the varactors is lower than what is used in the simulation, leading to the higher insertion loss. Moreover, we suspect that, the temperature for flip-chip bonding may be too high so that the characteristics of the ferroelectric thin film has changed, resulting in lowered tunability and thereby the reduced phase shift, which is less than 180°. Nevertheless, since the measured phase shift is as high as 161°, we successfully demonstrate that phase shifters with large amount of phase shift can be realized using MCPAN.

關鍵字(中)

★ 相位偏移器
★ 鐵電可變電容
★ 全通網路

關鍵字(英)

★ phase shifter
★ ferroelectric varactor
★ all-pass network

論文目次

國立中央大學 I
摘要 VI
Abstract VII
誌謝 IX
目錄 XI
圖目錄 XII
表目錄 XIV
第一章緒論 1
1–1 研究動機 1
1–2 文獻回顧 2
1–3 論文架構 4
第二章理論分析與設計 5
2–1 簡介 5
2–2 全通網路 6
2–3 磁耦合全通網路架構之分析 9
2–4 單級類比式相位偏移器之設計分析 16
第三章電路製作與量測結果 30
3–1 電路製程與製作 30
3–1–1 Metal1（電容下電極）製作流程 30
3–1–2 鐵電薄膜沉積 33
3–1–3 Metal2（電容上電極）製作流程 34
3–1–4 鐵電薄膜介電層製作流程 36
3–1–5 氮化矽保護層沉積與矽化鉻電阻製作流程 38
3–1–6 氮化矽保護層開洞製作流程 40
3–1–7 Metal3接腳層製作與電鍍流程 42
3–1–8 覆晶接合處電鍍與接腳層蝕刻 46
3–1–9 覆晶整合 49
3–2 量測結果 52
第四章結論 66
參考文獻 68
附錄 72
相位偏移器製作流程 72

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2019-3-28

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