博碩士論文 105521124 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:5 、訪客IP:35.172.150.239
姓名 曾聖翔(Sheng-Hsiang Tseng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用隨機性與均勻性檢測輔助增強晶圓圖系統性錯誤之解析
(Applications of Randomness and Homogeneity Test to Enhance the Systematic Error Resolution for Wafer Map Analysis)
相關論文
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器
★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
★ 陣列MiM電容的自動化佈局★ 陣列MiM電容的平衡接點之通道繞線法
★ 氣象資訊達人★ 嵌入式WHDVI多核心Forth微控制器之設計
★ 應用於電容陣列區塊之維持比值良率的通道繞線法★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 本篇論文為解決系統性錯誤在尺寸小的晶圓中判別力不足的問題,在九種系統性錯誤中針對其中六種有特別症狀的錯誤進行分割分析,分別分割成該特徵圖形之晶圓圖,並使用隨機性與均質性檢測來檢測分割後的晶圓以增強該特徵之系統性錯誤,藉由分割前與分割後的晶圓圖比較來觀察其判別效果。
藉由分割成各種不同的形狀後,我們藉由隨機性與均質性檢測,來實際檢測分割後的晶圓圖,在隨機性檢測上使用假設檢定的方式,在對立假設上假設是「是否是過度群聚」,檢定虛無假設使用單尾檢定,所以檢查B-score > 1.64,同樣,如果對立假設是「是否是反群聚」,檢定虛無假設使用單尾檢定,所以檢查B-score <- 1.64,如果對立假設是「是否是非隨機」,檢定虛無假設使用雙尾檢定,所以檢查B-score > 1.96 ,之後,即可畫出閘門圖(Gateway Diagram),將其分成五區。在均質性檢測則使用良率參數,針對切割後的良率相差大於一定閥值,來協助判別其晶圓圖錯誤。
針對不同的錯誤型態,使用不同的分割方式來判別,例如:藉由控制甜甜圈分割的半徑,來針對不同錯誤型態,藉以偵測損壞晶粒分布,經由切割後,再使用隨機性與均質性檢測方法來作判別。最後將檢測之結果合在一起,提高判別系統性錯誤之能力,進而提高良率及降低成本等目的。
摘要(英) The systematic error is hard to distinguish in small diesize wafer. In order to solve the problem, this paper analyze six kinds of symptomatic failure types among the nine kinds of systematic errors. Each of failure types have been cut into different shapes. The randomness and homogeneity test are used to enhance the detection resolution of systematic error after doing wafer partition. Then, we observe the resolution ratio in systematic error after doing partition.
After cutting into various shapes, we use the randomness and homogeneity test to test each wafer. In randomness test, the hypothesis test is used. If the alternative hypothesis is over-cluster, the null hypothesis is determined to use a one-tailed test. And, we will check whether B-Score is higher than the critical value 1.64 or not. If the alternative hypothesis is non-random, the null hypothesis is determined to use two-tailed tests. Then, check the absolute value of B-Score is higher than 1.96 or not. Finally, you can draw a gateway diagram and divide it into five blocks. In the homogeneity test, we choose the yield parameter to support us to analyze wafer. If the yield difference of wafer is higher than the threshold after doing partition, the wafer may have systematic error.
Different partition method is used to distinguish different failure types. For example, we change the radius of the donut partition wafer to detect the edge-ring failure type and the defect position. Then, the applications of randomness and homogeneity test is used for the wafer after doing partition. Finally, the results of the test are combined to enhance the systematic errors resolution, so as to improve the yield and reduce costs.
關鍵字(中) ★ 晶圓圖
★ 隨機性錯誤
★ 系統性錯誤
★ 良率
關鍵字(英) ★ Wafer map
★ Yield
★ Random errors
★ Systematic errors
論文目次 中文摘要 I
ABSTRACT II
致謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 1
1-1 研究背景與動機 1
1-2 文獻探討 2
1-3 論文目標 3
1-4 論文架構 4
第二章 研究方法 5
2-1 相關研究 5
2-2 迴力棒特徵圖 7
2-2-1 特徵參數NBD、NCL 8
2-2-2 特徵參數搜尋方式 8
2-2-3 特徵參數搜尋範例 9
2-2-4 損壞晶粒良率 YBD 11
2-3 迴力棒特徵圖共生效應 12
2-4 特徵參數 B-SCORE 13
第三章 分割晶圓圖隨機性與均勻性驗證 14
3-1 隨機性檢測 14
3-2 分割晶圓圖隨機性檢測 15
3-2-1 甜甜圈分割隨機性檢測 14
3-2-2 中國錢分割隨機性檢測 14
3-2-2 半圓分割隨機性檢測 14
3-2-2 扇形分割隨機性檢測 20
3-3 均勻性檢測 21
3.4 分割晶圓圖均勻性檢測 21
3-2-1 甜甜圈分割均勻性檢測 21
3-2-2 中國錢分割均勻性檢測 22
3-2-2 半圓分割均勻性檢測 22
3-2-2 扇形分割均勻性檢測 22
第四章 結合隨機性與均勻性分割真實晶圓圖之結果 23
4-1 甜甜圈分割真實晶圓檢測 23
4-2 中國錢分割真實晶圓檢測 26
4-3 半圓分割真實晶圓檢測 29
4-4 扇形分割真實晶圓檢測 31
第五章 結論 33
參考文獻 34
參考文獻 [1]J. E. Chen, M. J. Wang, Y. S. Chang, S. C. Shyu, and Y. Y. Chen, “ Yield Improvement by Test Error Cancellation ,” Proceedings of the Fifth Asian Test Symposium (ATS′96), pp.258-262, Nov. 1996.
[2]Q. P. He and J. Wang, "Fault Detection Using the k-Nearest Neighbor Rule for Semiconductor Manufacturing Processes," in IEEE Transactions on Semiconductor Manufacturing, vol. 20, no. 4, pp. 345-354, Nov. 2007.
[3] M. Wu, J. R. Jang and J. Chen, "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets," in IEEE Transactions on Semiconductor Manufacturing, vol. 28, no. 1, pp. 1-12, Feb. 2015.
[4]R. Baly and H. Hajj, "Wafer Classification Using Support Vector Machines," in IEEE Transactions on Semiconductor Manufacturing, vol. 25, no. 3, pp. 373-383, Aug. 2012.
[5] C. J. Huang, C. F. Wu and C. C. Wang, "Image processing techniques for wafer defect cluster identification," in IEEE Design & Test of Computers, vol. 19, no. 2, pp. 44-48, March-April 2002.
[6] M. Piao, C. H. Jin, J. Y. Lee and J. Byun, "Decision Tree Ensemble-Based Wafer Map Failure Pattern Recognition Based on Radon Transform-Based Features," in IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 2, pp. 250-257, May 2018.
[7] 林正田,「就隨機瑕疵源角度之晶圓圖分析」,國立中央大學,碩士論文,民國101年。
[8] 邱政文,「蝠翼:一個晶圓圖特徵化與產生的歸納模型」,國立中央大學,碩士論文,民國95年。
[9] 蕭寶威,「隨機缺陷分布之晶圓圖分析」, 國立中央大學,碩士論文,民國105年。
[10]葉昱緯,「迴力棒圖應用於真實量產晶圓圖」,國立中央大學,碩士論文,民國105 年。
[11]C. - K. Hsu, Lin, F., Cheng, K. - T. Tim, Zhang, W., Li, X., Carulli, J. M., and Butler, K. M., “Test data analytics - Exploring spatial and test-item correlations in production test data,” in IEEE International Test Conference (ITC), pp.1-10, Sep. 2013
[12]F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, “Learning from Production Test Data: Correlation Exploration and Feature Engineering,” in IEEE 23rd Asian Test Symposium, pp.236-241, Nov. 2014.
[13]F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, “Feature engineering with canonical analysis for effective statistical tests screening test escapes”, in International Test Conference(ITC), pp.1-10, Oct. 2014.
指導教授 陳竹一(Jwu-E Chen) 審核日期 2019-3-28
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明