晶圓圖缺陷分類與嵌入式系統實現

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姓名

李郁晨(Yu-Chen Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

晶圓圖缺陷分類與嵌入式系統實現
(Wafer Map Defect Pattern Classification and its Embedded System Implementation)

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至系統瀏覽論文 ( 永不開放)

摘要(中)

在半導體工業中，晶圓測試扮演不可或缺的一環，於生產的最後階段會進行不同電性的測試以確保產品的功能性，而測試結果再結合晶圓形狀所產生的圖形稱作晶圓圖(Wafer Map)，可以決定是否進行後續封裝等動作。然而，判斷產生的缺陷(defect)大多仰賴人工來執行，不僅耗費時間且需要經驗豐富之工程師。
本論文分別對網路上公開資料集WM-811K，以及公司合作所建立的資料集，進行晶圓圖缺陷分類。研究可分成兩個部分，一是神經網路的訓練，二是嵌入式系統上實現。神經網路部分，採用深度可分離卷積(depth separable convolution)的結構為基礎，設計出具有低參數量之神經網路，針對WM-811K中8類不同缺陷進行分類，最終可達97.01%準確度。在自行建立的資料集中，一共蒐集了16388張晶圓圖，定義21個缺陷類別，並對其進行擴增與分類，最終達87.4%準確度。系統方面，建立的資料使用MongoDB資料庫進行管理，放置於嵌入式板Jetson Nano，可連結遠端server進行訓練，回傳模型於嵌入式板執行推理(inference).此系統可以令使用者持續更新資料集，並對原模型進行優化，對於現今各公司晶圓缺陷定義不同，以及標注資料緩慢等問題，提供初步解決方案。

摘要(英)

In the semiconductor industry, wafer testing plays an indispensable role. There are different electrical tests in the final stages to ensure the functionality of the product. The results with the wafer shape is called Wafer Map. This map could decide whether to go to next step – package. However, most judgments of the defect rely on human to execute, which is time-consuming and requires experienced engineers.
In this paper, the wafer defect classification is carried out on the open dataset WM-811K. The dataset established by the cooperation with a company. The research can be divided into two parts, one is the training of neural network, and the other is implementation on embedded system. The neural network part is based on deep separable convolution. We design an architecture with low amount of parameters, which can classify the 8 different defects in WM-811K. It can finally achieve 97.01% accuracy. In the established dataset, a total of 16,388 wafers were collected, 21 defect categories were defined, and the data are augmented and classified. The final accuracy is 87.4% accuracy. On the system side, the established data is managed using the MongoDB database, placed on the embedded board Jetson Nano, which can be linked to remote servers for training and then it returns the model and performed on the embedded board to execute inference. This system enables users to continuously update the dataset and optimize the parameter model. It provides preliminary solutions to the different definition of wafer defects in today′s companies and solves the problem of slow labeling time.

關鍵字(中)

★ 晶片缺陷
★ 神經網路
★ 深度可分離卷積

關鍵字(英)

★ wafer defect
★ neural network
★ depthwise separable convolution

論文目次

摘要-----------------------------------------------I
ABSTRACT------------------------------------------II
1. 序論---------------------------------------1
1.1. 研究背景與動機------------------------------1
1.2. 論文架構-----------------------------------4
2. 文獻探討-----------------------------------5
2.1. 基於WM811K資料集---------------------------5
2.2. 基於自定義資料集----------------------------6
3. 網路模型設計與結果--------------------------9
3.1. 資料集-------------------------------------9
3.2. 資料前處理---------------------------------12
3.3. 數據增強策略-------------------------------16
3.4. 缺陷分類網路模型設計------------------------18
3.5. 訓練策略與結果-----------------------------24
4. 系統架構設計-------------------------------29
4.1. 產學合作----------------------------------29
4.2. 標注與訓練平台-----------------------------30
4.3. NVIDIA JETSON NANO執行結果----------------33
5. 結論--------------------------------------35
參考文獻------------------------------------------36

表目錄
表 1：CNN自編碼詳細參數 17
表 2：DWC1模型參數量 20
表 3：擴展模塊維度表 22
表 4：DWC2模型參數量 23
表 5：論文準確度比較表 25
表 6：DWC1參數量比較表 26
表 7：分割資料集準確度比較表 28
表 8：DWC2參數量比較表 28
表 9：NVIDIA JETSON NANO規格表 33
表 10：執行時間表 34

圖目錄
圖 1：晶圓測試階段示意圖 1
圖 2：CNN網路模型 3
圖 3：WM811K可視化與雷登變化特徵 5
圖 4：SVE流程圖 6
圖 5：自定義21類缺陷晶圓圖 7
圖 6：BIN2VEC結果示意圖 8
圖 7：WM-811K資料集 10
圖 8：WM-811K資料集數量結構 10
圖 9：自定義資料集(GUI可視化) 11
圖 10：資料轉換示意圖 12
圖 11：歐式距離轉換示意圖 13
圖 12：CHANNEL3晶圓圖 13
圖 13：RESIZED晶圓圖 14
圖 14：邊緣破碎圖 14
圖 15：修補後晶圓圖 15
圖 16：CNN自編碼器架構圖 16
圖 17：自編碼器生成晶圓圖 17
圖 18：旋轉生成晶圓圖 18
圖 19：標準CNN與深度可分離卷積架構圖 19
圖 20：DWC1網路架構 19
圖 21：RESIDUAL 與 INVERTED RESIDUAL 21
圖 22：DWC2模塊架構圖 22
圖 23：DWC2網路架構 23
圖 24：DWC1準確度訓練曲線 25
圖 25：DWC1 LOSS收斂曲線 25
圖 26：DWC2準確度訓練曲線 27
圖 27：DWC2 LOSS收斂曲線 27
圖 28：訓練流程圖 10
圖 29：MONGODB資料庫 31
圖 30：GUI介面圖 31
圖 31：系統資料傳遞圖 32
圖 32：NVIDIA JETSON NANO照片 34
圖 33：JETSON NANO執行結果圖 34

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2019-11-22

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