高速視覺檢測影像前處理硬體加速器

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姓名

何政倫(Jheng-Lun Ho) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

高速視覺檢測影像前處理硬體加速器
(A High Speed Image Preprocessing Hardware Accelerator for Vision Inspection)

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摘要(中)

機器視覺在工業自動化生產中應用相當廣泛，檢測環境往往會影響取像品質，導致後續影像處理和辨識效能的降低，進而影響自動化控制系統的整體性能。本研究研發一個高速視覺檢測系統的影像前處理硬體加速器，用以改善機器視覺系統的取像品質和效能。我們設計了自適應影像增強法ADPHE與自適應Wellner二值化硬體加速器。透過兩種影像前處理降低環境對檢測效率的影響，提升了影像品質，並達到高速的處理效能。為了滿足不同影像運算遮罩的需求，我們設計一個可動態調整遮罩大小的彈性化硬體架構，可藉由指令暫存器設定即可得到新的影像前處理硬體加速器，而不需更改電路。最後，我們以FPGA驗證影像前處理硬體加速器效能，本系統在127.81Mhz的時脈下，每秒能處理61張解析度為的影像，可滿足即時、高取像品質、彈性化的嵌入式視覺檢測應用。

摘要(英)

The machine vision is used in industrial automation production extensively, the inspection environment sometimes influences the imaging quality, so that the subsequent image processing and recognition performance are degraded, and then the overall performance of automatic control system is influenced. This study develops an image preprocessing hardware accelerator for high speed vision inspection systems to improve the imaging quality and performance of machine vision system. We design adaptive image enhancement ADPSHE and adaptive Wellner binarization hardware accelerator. The effect of environment on the inspection efficiency is reduced by two kinds of image preprocessing, the image quality is upgraded, and high speed processing performance is implemented. In order to meet the requirement for different image computing masks, an elastic hardware architecture which can adjust the mask size dynamically is designed, a new image preprocessing hardware accelerator can be obtained by command register setting without changing the circuit. Finally, the image preprocessing hardware accelerator performance is validated by FPGA. On the frequency of 127.81Mhz, this system can process 61 frames with images per second, applicable to real-time, high imaging quality and elastic embedded visual inspection.

關鍵字(中)

★ 硬體加速
★ 影像前處理

關鍵字(英)

論文目次

摘要 I
Abstract II
謝誌 III
目錄 V
圖目錄 VIII
表目錄 XI
第一章、緒論 1
1.1 研究背景 1
1.2 研究目的 3
1.3 論文架構 4
第二章、文獻回顧 5
2.1 影像對比增強技術 5
2.1.1 直方圖均衡化法 5
2.1.2 分段直方圖均衡化技術 7
2.1.3 直方圖裁剪均衡化技術 10
2.1.4 簡單直方圖修改法 13
2.1.5 自適應雙門檻值法 14
2.2 影像二值化技術 18
2.2.1 全域門檻值方法 18
2.2.2 自適應區域二值化法 19
2.3 MIAT設計方法論 23
2.3.1 IDEF0 24
2.3.2 Grafcet 27
2.3.3 硬體高階合成 30
第三章、影像前處理硬體加速器設計 32
3.1 系統架構 32
3.1.1 影像前處理模組 33
3.2 影像前處理IDEF0系統架構 33
3.2.1 ADPSHE模組 34
3.2.2 Wellner Binarization模組 35
3.3 影像前處理Grafcet 36
3.3.1 Bayer conversion Grafcet 37
3.3.2 RGB to Gray Grafcet 38
3.3.3 ADPSHE Grafcet 39
3.3.4 Wellner Binarization Grafcet 44
第四章、實驗結果 49
4.1 實驗平台 49
4.1.1 CMOS Sensor 49
4.1.2 MCU開發平台 50
4.1.3 FPGA開發平台 51
4.1.4 PC軟體驗證平台 52
4.2 影像增強品質評估實驗 53
4.2.1 絕對平均亮度誤差 53
4.2.2 標準差 54
4.2.3 熵 54
4.2.4 峰值訊號雜訊比 54
4.2.5 通用影像質量指數 55
4.2.6 結構相似性 56
4.2.7 影像增強評估結果 57
4.3 影像二值化實驗 61
4.3.1 文字辨識實驗 62
4.3.2 條碼辨識實驗 65
4.4 硬體合成與驗證 68
4.4.1 Bayer Conversion合成模組 69
4.4.2 RGBtoGray合成模組 69
4.4.3 ADPSHE合成模組 69
4.4.4 Wellner Binarization合成模組 71
4.4.5 硬體合成資源 72
4.4.6 軟硬體結果評估 74
4.5 硬體加速驗證 75
4.6 軟硬體系統平台驗證 77
第五章、結論與未來展望 81
5.1 結論 81
5.2 未來展望 82
參考文獻 83

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指導教授

陳慶瀚

審核日期

2018-7-3

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