CANopen硬體加速器設計與硬體實作

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姓名

曾元佑(Yuan-Yu Tseng) 查詢紙本館藏

畢業系所

資訊工程學系在職專班

論文名稱

CANopen硬體加速器設計與硬體實作
(Design and Implementation of CANopen Hardware Controller With Industrial Ethernet)

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[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2025-7-9以後開放)

摘要(中)

工業 4.0 推動智慧製造的演進變革，透過工業互聯網路串連製造系統中的感測器、生產機台與可程式化控制設備，讓大量的生產數據得以即時收集並且傳遞到生產監控系統進行後續的分析與處理。但是工廠內的生產機台與控制設備有著各自不相容的通訊協定，這些無法彼此溝通的通訊協定往往造成資料交換的傳輸瓶頸與衍生網路設備難以有效管理的問題。因此本研究提出以硬體加速的方式，設計 CANopen 通訊協定的硬體加速器，利用乙太網路為資料傳輸介面，透過 UDP 封包傳輸 CANopen 訊息，解決不同設備之間資料交換的問題，也讓網路設備得以有效地管理。本研究利用 Intel Altera FPGA作為實驗平台，以 MIAT 硬體設計方法論設計與實作 CANopen slave 通訊協定，搭配影像串流傳輸的應用來驗證網路資料封包的高速傳輸效能。

摘要(英)

Industry 4.0 promotes the evolution of smart manufacturing. Sensors, production equipment and programmable logic controllers in manufacturing systems connect through industrial internet and allow a large amount of production data can be collected in real-time
and passed to the production monitoring system for subsequent analysis and processing.
However, the production equipment in the factory have their own incompatible communication protocols. Different communication protocols that cannot communicate with
each other often cause the transmission bottleneck` of data exchange and the problem that derivative the network equipment are difficult to manage effectively. Therefore, this study proposes to design the hardware accelerator of the CANopen communication protocol using Ethernet as the data transmission interface. The CANopen messages are transmitted through UDP packets, which solve the problem of data exchange between different devices and also allow network devices to be effectively managed. This study uses Intel Altera FPGA as the experimental platform and use the MIAT hardware design methodology to design and implement the CANopen slave controller. With the application of video streaming to verify the high-speed transmission performance of network data packets.

關鍵字(中)

★ CANopen網路通訊協定
★ FPGA硬體實作
★ MIAT方法論

關鍵字(英)

★ CANopen
★ FPGA design
★ Grafcet

論文目次

摘要 ......................................... I
Abstract...................................... II
謝誌 ......................................... III
目錄 ......................................... IV
圖目錄 ....................................... VI
表目錄 ....................................... IX
第一章、緒論 ................................. 1
1.1 研究背景....................................1
1.2 研究目的....................................4
1.3 論文架構....................................4
第二章、技術回顧 ............................. 5
2.1 CANopen 通訊協定概述........................5
2.2 CANopen 通訊物件............................6
2.3 CANopen 物件字典............................8
2.4 SDO Protocol................................9
2.5 PDO Protocol................................12
2.6 Network Management Protocol.................16
2.7 Synchronous Protocol........................18
2.8 Time Stamp Protocol ........................19
2.9 Emergency Protocol .........................20
2.10 Node-Guarding Protocol ....................20
2.11 Heartbeat Protocol ........................22
第三章、 CANopen slave 硬體加速器架構設計 ..... 23
3.1 CANopen slave 應用系統架構..................23
3.2 MIAT 嵌入式硬體設計方法論...................24
3.2.1 IDF0 階層式模組化設計.....................25
3.2.2 Grafcet 離散事件建模 .....................28
3.2.3 硬體高階合成..............................31
3.3 CANopen slave 硬體加速器 IDEF0..............32
3.3.1 CANopen slave 離散事件模型................33
3.3.2 Message parser 離散事件模型 ..............35
3.3.3 CANopen protocol handler 離散事件模型.....35
3.3.4 Message sender 離散事件模型...............37
3.3.5 Object service handler IDEF0 .............38
3.3.6 Object service handler 離散事件模型 ......39
3.3.7 NMT state machine 離散事件模型 ...........40
3.3.8 Boot-up event handler 離散事件模型 .......41
3.3.9 Heartbeat event handler 離散事件模型......42
3.3.10 SYNC event handler 離散事件模型..........43
3.3.11 Emergency event handler 離散事件模型.....45
3.3.12 Object dictionary handler 離散事件模型 ..46
3.3.13 SDO service handler 離散事件模型.........47
3.3.14 PDO service 離散事件模型.................48
第四章、硬體驗證與實驗結果 ................... 51
4.1 實驗平台....................................51
4.1.1 FPGA 開發平台.............................51
4.1.2 CMOS Sensor...............................52
4.1.3 PC 軟體驗證平台 ..........................53
4.2 系統功能模組硬體合成........................53
4.3 串流影像資料傳輸驗證........................54
第五章、結論與未來展望 ....................... 63
5.1 結論........................................63
5.2 未來展望....................................63

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指導教授

陳慶瀚(C.H. Chen)

審核日期

2020-7-10

推文