高壓半導體元件之功率電路設計論

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姓名

盧登峰(Deng-Fong Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高壓半導體元件之功率電路設計論
(Power circuit design of high-voltage semiconductor components)

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至系統瀏覽論文 (2026-3-11以後開放)

摘要(中)

包絡跟踪（ET）技術為具有高峰均比（PAR）信號的功率放大器（PA）提供了實現高效率的潛力。低失真，高效率和寬帶寬的包絡放大器是廣泛應用於包絡跟踪的關鍵組件。
本文介紹了一種用於包絡放大器的線性輔助切換式降壓轉換器的設計。為了有效利用降壓轉換器的高效率和線性放大器的寬帶寬能力，在這項研究中採用了這兩種電路的並聯組合。提出了一種新穎的電流檢測恆定導通時間（COT）控制器來協調這種混合電源。這種組合主要使切換式轉換器能夠高效地提供PA所需的平均功率，而寬帶線性放大器則提供了廣泛的動態電壓。該技術提高了包絡放大器的效率，特別是對於需要具有較高帶寬信號的高PAR的應用。
使用LTE下行鏈路信號，包絡放大器的測量結果表明，輸出功率為10 W時，效率約為77％。通過使用GaN PA演示了整個ET系統。對於具有20 MHz帶寬和PAR為8.0 dB的LTE調製信號，在5 W的平均輸出功率和10.1 dB的增益下，放大器的測量平均功率增加，效率達到45％以上。在20 MHz的偏移頻率下，相鄰通道功率比為-48 dBc時，測得的歸一化RMS誤差低於2.1％。

摘要(英)

Envelope tracking (ET) technology provides the potential for achieving high efficiency in power amplifiers (PAs) with high peak-to-average ratio (PAR) signals. Envelope amplifiers with high fidelity, high efficiency, and wide bandwidth are critical components for the widespread application of envelope tracking.
This paper presents the design of a linear-assisted switching buck converter for use in an envelope amplifier. To effectively leverage the high efficiency of buck converters and the wide bandwidth capabilities of linear amplifiers, a parallel combination of these two devices is employed in this work. A novel current-sense constant-on-time (COT) controller is proposed to coordinate this hybrid power supply. The combination mainly enables the switching converter to provide the average power required by the PA with high efficiency, while the wideband linear amplifier provides a wide range of dynamic voltages. The technique improves the efficiency of the envelope amplifier, especially for applications requiring high PAR with wider bandwidth signals.
Measurement of the envelope amplifier showed an efficiency of approximately 77 % with 10 W output power using LTE downlink signals. The overall ET system was demonstrated by using a GaN PA. The measured average power-added efficiency of the amplifier reached above 45 % for an LTE modulated signal with 20 MHz bandwidth and PAR of 8.0 dB, at an average output power of 5 W and gain of 10.1 dB. The measured normalized RMS error is below 2.1% with adjacent channel leakage ratio of -48 dBc at an offset frequency of 20 MHz.

關鍵字(中)

★ 功率電路
★ 高壓半導體元件

關鍵字(英)

★ Power circuit
★ high-voltage semiconductor components

論文目次

摘要 i
Abstract ii
致謝 iii
Contents iv
Figure Captions vi
Table Captions vii
Chapter 1 Introduction 1
1-1 Research Background 1
1-2 Literature Review 2
1-3 Thesis Organization 5
Chapter 2 Gate drive circuit architecture and analysis 7
2-1 Low-side driver circuit 7
2-2 High-side driver circuit 7
2-3 Hard-switching 9
2-4 Soft-switching 10
2-5 Loss analysis 11
Chapter 3 Linear-assisted Switching Buck Converter Design verification and application 15
3-1 Synchronous control principle and operation of buck converter 15
3-2 Controller Design Considerations for Optimal Efficiency 17
3-3 Performance Comparisons between the Hysteretic and COT Controller 23
3-4 Design of Current-sense COT Controller 28
Chapter 4 Circuit Implementation and Measurement Results 31
4-1 EA Implementation and Test 31
4-2 ET system test 37
Chapter 5 Conclusion 43
Reference 44

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指導教授

夏勤(Chin Hsia)

審核日期

2021-3-25

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