博碩士論文 106521027 詳細資訊




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姓名 李怡瑩(Yi-Ying Li)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 用泰勒級數求四面體內部向量及三維元件模擬
(Finding internal vector from the Taylor series in tetrahadron element for 3D semiconductor device simulation)
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摘要(中) 本篇論文中,主要是利用泰勒級數法開發一個四面體網格模組,並且用來模擬元件的特性,而為了能夠使模組可以以任意四面體當基本網格,我們選擇以重心來開發模組。根據我們的分析,在與其他方法進行比較後,我們發現泰勒級數法能夠完美的克服以往所遇見的問題,故我們選擇泰勒級數法來求得方程式裡所需要的四面體內部電場向量,完成程式模組後,設定四面體座標與電位,並且驗證此四面體的電場、電子流與電洞流,再來,將五顆四面體組合成一個單顆立方體電阻,比較其模擬值與計算出的理論值,以確認模組開發的精確性。最後,嘗試以兩種不同方法串接多顆立方體電阻時所發現的誤差,並探討其原因。
摘要(英) In this thesis, we develop a tetrahedron element module by using the Taylor series and use it to simulate 3D semiconductor device. In order to enable this module to be applied to arbitrary tetrahedron, we choose barycenter method to develop the module. According to our analysis, after comparing with other methods, we find that the Taylor series can overcome the problem in the past, so we choose the Taylor series to find the internal electric field vector. After completing the module, set the coordinates and potentials of the tetrahedron, and verify the electric field, the electron current density, and the hole current density. Then, the five tetrahedrons are combined into a cube resistor, and compare the simulated value with the theoretical value to confirm the accuracy of the module development. Finally, try to find the error when connecting multiple cube resistors in two different ways and discuss the reason.
關鍵字(中) ★ 泰勒級數
★ 半導體元件
★ 元件模擬
關鍵字(英)
論文目次 摘要...................................................i
Abstact...............................................ii
圖目錄.................................................v
表目錄................................................vii
第一章 簡介.............................................1
第二章 泰勒級數法與四面體模型開發.........................4
2.1 基本立方體網格結構分析...............................4
2.2 平面法與軸線法之缺點.................................7
2.3 泰勒級數法求其內部向量..............................10
第三章 泰勒級數法與四面體模型驗證........................22
3.1 四面體模組電場驗證..................................22
3.2 四面體模組電子流密度與電洞流密度驗證..................25
3.3 簡單立方體電阻模擬..................................30
第四章 多顆六面體網格問題探討............................33
4.1 多顆電阻模擬驗證....................................33
4.2 兩顆六面體兩種接法電阻比較...........................35
4.3 串接兩顆封閉面的探討................................39
第五章 結論............................................43
參考文獻...............................................44
參考文獻 [1]Y. M. Li, “Research on Development of Computer Simulation Methods for Semiconductor Devices and Nanostructures.” D. S. Thesis, Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China, 2000.
[2]C. C Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “3-D Numerical Device Simulation Including Equivalent-Circuit Model”, IEDMS, 2002.
[3]G. W. Tang, “Generation of Tetrahedral/Prismatic Meshes and Its Applications in Microchannel Flows”, D. S, Thesis, Institute of AA, National Cheng Kung University, Taiwan, Republic of China, 2006.
[4]D. A Neamen, Semiconductor physics and devices, 3rd ed. McGraw-Hill Companies Inc., New York, 2003.
[5]R. E. Bank, D. J. Rose, and W. Fichtner, “Numerical methods for semiconductor device”, IEEE Trans, Electron Devices, vol. 30, no. 9, Sep. 1983.
[6]Y. Q. Hong, “Development of tetrahedron circumcenter element and its applications to 3D semiconductor device simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2017.
[7]J. H. Seo, Y. J. Yoon, S. Lee, J. H. Lee, S. Cho, and I. M. Kang, “Design and Analysis of Si-Based Arch-Shaped Gate-All-around (Gaa) Tunneling Field-Effect Transistor (T fet)”, Current Applied Physics, Vol. 15, pp. 208-212, 2015.
[8]D. G. Shih, “Finding internal vector from the plane equation and axis method in tetrahedron element for 3D semiconductor Device Simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018.
[9]M. J. Zeng, “Development of Triangular element and its applications to arbitrary 2D semiconductor device” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2014.
[10]B. Adolph and F. Bechstedt, “Ab initio second-harmonic susceptibilities of semiconductors : Generalized tetrahedron method and quasiparticle effects”, Physical Review B, 1998.
[11]K. Y. Hung, “Integration of Band Solver and BILU Solver for 3-D Device Simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2012.
[12]D. M. Wood, Alex Zunger, and R. De Groot. “Electronic structure of filled tetrahedral semiconductors.” Physical Review B 31.4 1985.
[13]J. S. Zhao, F. L. Chu and Z. J. Feng, “Kinematics of Spatial Parallel Manipulators with Tetrahedron Coordinates”, IEEE Trans, Robotics, vol. 30, no. 1, pp. 233-243, Feb. 2014.
[14]H. C. Casey, Devices for integrated circuits : silicon and III-V compound semiconductors. New York: John Wiley, 1999.
[15]M. Putti and C. Cordes, “Finite Element Approximation of The Diffusion Operator on Tetrahedral”, Society for Industrial and Applied Mathematics vol. 19, no. 4, pp. 1154-1168, 1998.
[16]W. H. Chiu, “Finding internal vector from the edge vector in arbitrary tetrahedron element for 3D semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, pp. 29-31, 2017.
[17]M. C, Huang, “Area-Partition Problems in 2-D Semiconductor Device Simulation.” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2015.
[18]L. T, Wang, “Development of point-added cube element and its application to Semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018.
指導教授 蔡曜聰 審核日期 2019-7-19
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