具資料及邊緣符碼間干擾補償之28Gbps四階脈波振幅調變自適應等化器

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謝文軒(Wen-Hsuan Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具資料及邊緣符碼間干擾補償之28Gbps四階脈波振幅調變自適應等化器
(A 28 Gbps PAM-4 Adaptive Equalizer with Data and Edge ISI Compensation)

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至系統瀏覽論文 (2025-7-31以後開放)

摘要(中)

近年來，物聯網(IoT)、人工智慧(AI)和5G行動網路的興起，帶動資料傳遞頻寬提升，然而，資料經過通道會受到符碼間干擾(Inter-symbol interference, ISI)影響，導致訊號完整度下降，因而帶動資料格式與補償電路的發展，相較於常見的不歸零式資料(Non-Return-to-Zero, NRZ)，四階脈波振幅調變(Pulse Amplitude Modulation 4, PAM-4)資料僅需較小傳輸頻寬的優點，使其獲得高速傳輸規格的青睞。另一方面，隨著通道衰減提升，等化器被廣泛應用於接收端以補償通道衰減，使其成為目前主流研究趨勢之一。
傳統決策回授等化器利用決策器判斷資料，並延遲適當時間消除資料位元週期長度的符碼間干擾，因為不能隨時改變其補償量的大小，只能針對資料或邊緣的符碼間干擾進行消除，故無法同時兼顧眼高和眼寬，本論文提出傳輸閘決策回授等化器(Transmission Gate Decision Feedback Equalizer, TG-DFE)，能夠在一個迴路裡同時補償資料和邊緣符碼間干擾，並且降低決策回授等化器因迴路延遲增加影響資料抖動的問題，搭配連續時間線性等化器(Continuous Time Linear Equalizer, CTLE)同時進行補償，利用自適應演算法針對臨界電壓、CTLE和TG-DFE的補償權重進行收斂，使等化器在不同通道衰減下都能正確的補償，此作法不僅降低硬體複雜度和功率消耗，也大幅提升等化器的使用彈性。
本論文使用TSMC 40 nm (TN40G) 1P10M之CMOS製程實現，電路操作電壓為0.9 V，輸入之資料速率為28 Gbps，輸入時脈為14 GHz。通道衰減範圍從12 dB到16 dB，在通道衰減12 dB時，等化後資料的峰對峰值抖動量為50.4 ps，方均根抖動量為14.7 ps；在通道衰減16 dB時，等化後資料的峰對峰值抖動量為51.6 ps，方均根抖動量為15.2 ps。在通道衰減16 dB時，整體功率消耗為95.9 mW，其中CTLE以及TG-DFE之等化器功率消耗為65.3 mW，自適應機制電路之功率消耗為30.6 mW，晶片面積為1.15 mm2，其中核心電路面積為0.09 mm2。

摘要(英)

In recent years, with the rise of Internet of Things (IoT), Artificial Intelligence (AI) and 5th generation mobile networks (5G), the bandwidth of data transmission has been increasing day by day. However, the signal integrity of high speed data gets worse after passing through the channel because of the inter-symbol interference (ISI). As a consequence, the data format and compensation circuits become popular. Morover, because the four level pulse amplitude modulation (PAM-4) data requires lower bandwidth, compared with non-return-to-zero (NRZ) data, it has been held in high regard by the high speed transmission protocols. On the other hand, the equalizer is used widely at receiver to compensate the attenuate signal, for the channel loss becomes higher and higher. Therefore, the equalizer turns into one of the mainstram research topic.
This thesis presents an innovative transmission gate decision feedback equalizer (TG-DFE) with data and edge ISI compensation. Both data and edge ISI can be eliminated simultaneously in one loop. With this architecture, the eye width of the data will have better immunity to the loop delay variation. This thesis implements continuous time linear equalizer (CTLE) and 1-tap TG-DFE to compensate the attenuate signal. Besides, this work includes the adaptive system which can optimize the threshold voltage (Vth) and the compensation of CTLE and TG-DFE. With the adaptive system, this circuit can work correctly under different channel loss. In this way, the complexity and power consumption of circuits are reduced, and the flexibility of adaptive equalizer is improved.
The fabricated chip was implemented by TSMC 40 nm (TN40G) 1P10M CMOS process. When the channel loss is 12 dB, the peak-to-peak jitter of equalized data is 50.4 ps and the root mean square (RMS) jitter is 14.7 ps. When channel loss is 16 dB, the peak-to-peak jitter of equalized data is 51.6 ps and the RMS jitter is 15.2 ps. The power consumption is 95.9 mW at a supply voltage of 0.9 V and the channel loss of 16 dB. The entire equalizer and the overall adaptative system utilize 65.3 mW and 30.6 mW of power, respectively. The chip area is 1.15 mm2 and the core area is 0.09 mm2.

關鍵字(中)

★ 等化器
★ 四階脈波振幅調變
★ 連續時間線性等化器
★ 決策回授等化器

關鍵字(英)

★ Equalizer
★ PAM-4
★ CTLE
★ DFE

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 基本觀念 4
2.1.1 隨機二位元資料特性 4
2.1.2 資料編排形式 5
2.1.3 四階脈波振幅調變 5
2.1.4 傳輸線理論 6
2.2 單一位元脈衝響應與等化器之關係 10
第3章等化器之設計及其自適應控制機制 16
3.1 等化器的種類 16
3.1.1 連續時間線性等化器(CTLE) 17
3.1.2 決策回授等化器(DFE) 18
3.1.3 前饋式回授等化器(FFE) 19
3.1.4 等化器在系統中的應用 20
3.2 自適應機制的種類 21
3.2.1 最小均方演算法(LMS) 21
3.2.2 Sign-Sign LMS演算法之自適應決策回授等化器 24
3.2.3 Sign-Sign LMS之使用條件 26
3.2.4 逼零演算法(Zero-Forcing Algorithm) 29
3.3 等化器文獻探討 30
3.3.1 多級決策回授等化器[20] 30
3.3.2 無限脈衝響應決策回授等化器[21] 31
3.3.3 資料邊緣決策回授等化器[22] 31
3.4 比較與討論 32
第4章具自適應之連續時間線性等化器與傳輸閘決策回授等化器設計與實現 34
4.1 電路架構 34
4.2 操作說明 36
4.2.1 傳輸閘決策回授等化器(TG-DFE)補償分析 36
4.2.2 不同等化器補償情況 38
4.3 行為模擬 40
4.4 連續時間線性等化器(CTLE) 40
4.5 一級傳輸閘決策回授等化器(1-Tap TG-DFE) 42
4.6 自適應系統(Adaptive System) 46
4.6.1 訊號序列偵測器(Data Pattern Detector) 47
4.6.2 自適應演算系統(Adaptive Algorithm) 48
4.6.3 增益調整電路 (Gain Adjustment Circuit) 49
4.6.4 迴路切換機制(Switch Mechanism) 51
4.7 模擬結果 52
4.7.1 通道模型 52
4.7.2 具自適應之28 Gbps等化器模擬 54
4.7.2.1 佈局前之短通道模擬 54
4.7.2.2 佈局前之長通道模擬 56
4.7.2.3 佈局後之短通道模擬 58
4.7.2.4 佈局後之長通道模擬 60
4.7.3 模擬結果分析和比較 62
4.7.4 DT-DFE和TG-DFE的模擬結果分析 64
第5章晶片佈局與實驗結果 69
5.1 電路佈局 69
5.1.1 晶片封裝 69
5.1.2 佈局規劃與電源規劃 71
5.2 量測考量 72
5.2.1 量測環境 72
5.2.2 高頻輸出緩衝器 73
5.2.3 高頻時脈輸入端 74
5.2.4 M8048A ISI通道 75
5.3 晶片與印刷電路板照相圖 76
5.4 量測結果 77
5.5 規格比較表 79
第6章結論 80
6.1 結論 80
6.2 未來研究方向 81
參考文獻 82

參考文獻

[1] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[2] VESA DisplayPort Standard, Version 1, Revision 2, Jan. 2010.
[3] Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013.
[4] Serial ATA International Organization, Serial ATA Revision 3.0, SATA-IO, 2009.
[5] PCI Express® Base Specification, Revision 2.1, PCI-SIG, 2010.
[6] Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O and 56G+ bps, Revision 4.0, Common Electrical-IO, 2017.
[7] Behzad Razavi, “Basic concepts,” in Design of Integrated Circuits for Optical Communications, 1st ed. New York, NY, USA: McGraw-Hill, 2003, ch. 2, sec. 1, pp. 8–9.
[8] J. Lee et al., “Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2061–2073, Sep. 2015.
[9] S. H. Hall, G. W. Hall, and J. A. McCall, “The Importance of Interconnect Design,” in High-speed digital system design - A handbook of interconnect theory and design practices, 1st ed. New York, NY, USA: John-Wiley, 2002, ch. 1, sec. 1, pp. 1–4.
[10] M. Li, “Deterministic Jitter (DJ) Definition and Measurement Method: An old problem revisited,” Altera Corporation, San Jose, California, USA, 2009. [Online]. Avaliable: http://www.ieee802.org/3/ba/public/jan09/li_01_0109.pdf
[11] SHF Communication Technologies AG. Application Note AN-JITTER-1-Jitter Analysis using SHF 10000 Series Bit Error Rate Testers, (2005). [Online]. Avaliable: https://www.shf-communication.com/wp-content/uploads/appnotes/shf_app_note_jitter-analysis-using_10000_series_bert.pdf
[12] S. Wang, HFAN-03.0.2: Optical receiver performance evaluation Maxim Integrated application note 1938, 2003.
[13] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, and Y.-F. Lin, “A 5-Gb/s inductorless CMOS adaptive equalizer for PCI express generation II applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 5, pp. 324–328, May 2010.
[14] J. W. Jung and B. Razavi, “A 25 Gb/s 5.8 mW CMOS equalizer,” in IEEE ISSCC Dig. Tech. Papers, pp. 44–45, Feb. 2014.
[15] C. A. Belfiore and J. H. Park, “Decision feedback equalization,” Proc. of the IEEE, vol. 67, pp. 1143–1156, Aug. 1979.
[16] J. Proakis, “Adaptive Decision-Feedback Equalizer,” in Digital Communication, 5th ed. New York, NY, USA: McGraw-Hill, 2007, ch. 10, sec. 2, pp. 705–706.
[17] R. W. Lucky, ‘‘Techniques for adaptive equalization of digital communication systems,’’ Bell Syst. Tech. J., vol. 45, no. 2, pp. 255–286, Feb. 1966.
[18] 陳俊諺, “以逼零演算法實現無外部校正之單一自適應系統之 5 Gbps 全速率連續時間線性等化器與決策回授等化器,” 碩士論文, 國立中央大學, 2017.
[19] Y. Hidaka, W. Gai, et al., “A 4-channel 1.25-10.3 Gb/s backplane transceiver macro with 35 dB equalizer and sign-based zero-forcing adaptive control,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3547–3559, Dec. 2009.
[20] J. Im et al., “A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3486–3502, Dec. 2017.
[21] S. Shahramian, B. Dehlaghi, and A. C. Carusone, “Edge-based adaptation for a 1 IIR + 1 discrete-time tap DFE converging in 5 µs,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3192–3203, Dec. 2016.
[22] Seok Kim et al., “A 6.4-Gb/s voltage-mode near-ground receiver with a one-tap data and edge DFE,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 6, pp. 438–442, Jun. 2014.
[23] Y.- Shunbin Li, Yingtao Jiang, and Peng Liu, “An adaptive PAM-4 analog equalizer with boosting-state detection in the time domain,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 25, no. 10, pp. 2907–2916, Oct. 2017.
[24] B. Nikolic et al., “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884, Jun. 2000.
[25] 許馥淳, “應用在序列傳輸系統之10-Gbps離散時間適應性等化器,” 碩士論文, 國立交通大學, 2009.
[26] 陳紫宜, “具高通濾波補償之10 Gb/s全速率自適應四階脈波振幅調變等化器,” 碩士論文, 國立中央大學, 2019.
[27] Keysight, “M8048A ISI Channels - Data Sheet”.
[28] H. Miyaoka et al., “A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2015, pp. 245–248.
[29] C.-T. Hung, Y.-P. Huang, and W.-Z. Chen, “A 40 Gb/s PAM-4 receiver with 2-tap DFE based on automatically non-even level tracking,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2018, pp. 213–214.
[30] P. J. Peng, J. F. Li, L. Y. Chen, and J. Lee, “A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 110–111.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2020-8-13

推文