用於類比電路仿真器的波動數位濾波器之硬體最佳化方法

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姓名

李孟霖(MENG-LIN LI) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於類比電路仿真器的波動數位濾波器之硬體最佳化方法
(Resource Optimization for Hardware Generation of WDF-based Circuit Emulators)

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摘要(中)

隨著製程進步，目前的超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC ) 已成為設計的主流，由於一個系統通常同時包含數位電路與類比電路，因此類比/混合訊號(Analog/mixed-signal, AMS)電路的驗證在開發晶片的流程中變的重要許多。在這篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路轉成對應的數位電路來進行仿真。此方法使用入射波與反射波的方式描述電路特性，可以將每個類比元件對應至波動數位濾波器架構的數位元件，達成與數位電路一起模擬的目標。
本論文根據WDF架構仿真流程之相關文獻，建立一個將類比電路自動轉換為WDF結構的數位電路的仿真環境，並使用基於敏感度的方法，將各個配線器的γ值變化表示為與輸入電壓相關的公式，取代以往需要冗長運算時間的查表以及內插方法。而針對電路優化方面，我們運用了整數線性規劃演算法，得出最小所需配線器數量，並套用仿射算數模型，在保有一定精準度下，算出所需的最小位元長度，以此來縮小產生的電路面積。由實驗結果可看出，綜合了以上方法，所產生的WDF類比仿真電路比以往在速度及面積上都有大幅的優化，且自動化環境也使得使用者在進行類比仿真時更加迅速及便利。

摘要(英)

With the advance of semiconductor technologies, the design of Very-Large-Scale Integration (VLSI) circuits becomes more complex. System-on-Chip (SOC) has become the main stream of VLSI design style . Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter(WDF) theorem to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits.
Based on the previous studies for the simulation process of WDF architectures, this thesis presents an automatic environment for converting analog circuits into WDF structures. Using the sensitivity-based method, the change of γ value at each adaptor becomes a formula related to the input voltage, This approach successfully avoids long calculation time by replacing the look-up table and interpolation method. In order to minimize hardware resource, integer linear programming algorithm is used to obtain the minimum number of required adaptors, The affine arithmetic model is also applied to calculate the minimum bit length with certain precision. As shown in the experimental results combining the proposed methods, the generated WDF circuits are greatly improve in terms of speed and area. The automation environment also improves the convenience for users to do analog emulation

關鍵字(中)

★ 類比電路
★ 仿真
★ 數位波動濾波器

關鍵字(英)

論文目次

摘要 i
Abstract v
致謝 vi
目錄 vii
圖目錄 ix
表目錄 xiii
1 第一章、緒論 1
1-1 前言 1
1-2 相關研究 4
1-2-1 場列式可程式類比陣列(FPAA) 4
1-2-2 可程式化類比元件陣列(PANDA) 6
1-3 論文結構 8
2 第二章、背景知識 9
2-1 數位濾波器(Digital Filter)模型 9
2-2 波動數位濾波器(Wave Digital Filter) 11
2-2-1 波動數位濾波器模型 11
2-2-2 配線器(Adaptor) 14
2-2-3 非線性半導體場效電晶體模型(MOSFET) 18
2-2-4 新式J型配線器(J-type adaptor) 19
2-3 WDF的硬體實作方法 22
3 第三章、硬體設計最佳化方法 24
3-1 類比仿真器的仿真流程 24
3-2 硬體實現平台 26
3-3 基於敏感度的WDF運算方法 27
3-4 位元長度最佳化方法 27
3-4-1 整數部分位元優化 29
3-4-2 分數部分位元優化 29
3-4-3 更精確的位元長度調整 31
3-5 最少配線器及硬體共用的最佳化方法 32
3-5-1 基礎硬體共用 32
3-5-2 整數線性規劃的最小配線器最佳化 33
3-6 自動化硬體生成環境 37
3-7 硬體架構 39
4 第四章、實驗結果 41
4-1 實驗環境 41
4-2 T型橋式電路(Bridged-T) 41
4-3 二階放大器(Two Stage OPA) 43
5 第五章、結論與未來工作項目 46
6 參考文獻 47

參考文獻

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指導教授

周景揚

審核日期

2019-8-19

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