摘要(英) |
Under the process variation, the yield of the chips which are at the different locations with different characterization is in the same wafer. With the entry of the nanometer era, the wafer defect patterns become more various. The easiest way to observe these defect patterns due to process variation is from the viewpoint of the wafer map. In previous research, we use the Poisson distribution model to generate and analyze the homogeneous random defect wafer map. In this paper, we use the Bat-wing model to generate the nonhomogeneous random defect wafer map and calculate the distance between the wafer center and every bad die, then we can get the mean (DistanceMean) and the standard deviation (DistanceSTD) of the distance.
Next, we use the actual wafer map data, which is the WM-811K wafer database released by TSMC to calculate DistanceMean and DistanceSTD. The ring partition is based on these two parameters. The wafer map is partitioned into three zones which are out-ring, inner-ring, and circle. The size of the three zones is dynamic due to the difference between the number and the distribution of bad die. Afterward, we calculate the ratio of the bad die and the defective rate of each zone. We analyze and use these parameters to help us classify the nine failure patterns which are Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-full, Random, none. |
參考文獻 |
[1] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[2] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[3] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[4] Jwu E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps”, VLSI Test Technology Workshop (VTTW), Jul. 2019.
[5] Mengying Fan, Qin Wang, and Ben van der Waal, “Wafer defect patterns recognition based on OPTICS and multi-label classification”, IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), pp. 912-915, Oct. 2016.
[6] Bing Liu, “A Fast Density-Based Clustering Algorithm for Large Databases”, International Conference on Machine Learning and Cybernetics, pp. 996-1000, Aug. 2006.
[7] Cheng Hao Jin, Hyuk Jun Na, Minghao Piao, Gouchol Pok, and Keun Ho Ryu, “A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map”, IEEE Transactions on Semiconductor Manufacturing, Vol. 32, pp. 286-292, May. 2019.
[8] 邱政文, “Bat-Wing: An Inductive Model for Wafer Map Characterization and Generation”, 碩士論文, 中央大學, 2006.
[9] 林威沅, “Verification of B-score Randomness by Synthetic Random Wafer Maps and Application to Special Patterns”, 碩士論文, 中央大學, 2019.
[10] 侯睿軒, “Model Refinement for the Classifier of the Spatial Pattern Randomness”, 碩士論文, 中央大學, 2019.
[11] 黃昱凱, “Acceleration Core for the Calculation of the Randomness Features of Wafer Maps”, 碩士論文, 中央大學, 2019.
[12] 曾聖翔, “Applications of Randomness and Homogeneity Test to Enhance the Systematic Error Resolution for Wafer Map Analysis”, 碩士論文, 中央大學, 2019.
[13] 呂東穎, “Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification”, 碩士論文, 中央大學, 2019.
|