||The design of analog/mixed-signal (AMS) integrated circuits is getting complex as technology advances. Speeding up the simulation involving with digital and analog circuits becomes a key to solve the system verification issues for SOC designs. Building their behavioral models for analog circuit blocks by hardware description language is an efficient approach for verifying AMS systems. If each analog circuit can be transformed into its corresponding behavioral model automatically, the simulation time for the analog part can be greatly reduced. Therefore, an efficient structure analysis flow is desired to automatically extract the building blocks, no matter it is an analog block or digital block, in a mixed-signal design based on the given circuit netlist. Using a special encoding scheme, the digital and analog blocks in the netlist can be identified quickly and replaced automatically by the corresponding behavior models built in the library. However, in previous works, different circuits may have duplicate structure in digital circuit analysis. In analog circuit analysis, the identified blocks may have overlap issues, too. In this thesis, we extend the previous structure analysis platform to consider these issues. In the case of duplicate structure, additional encoding is added in digital circuit analysis to verify the accuracy of the port orders of the circuit. In analog circuit analysis, a bottom-up hierarchical structure recognition approach is proposed to accurately determine which the circuit structure belongs to. This approach solves the structure overlap problem and raise the abstraction level of the identified models simultaneously. As shown in the experiments, the efficiency and accuracy of the identification results can be improved to reduce the extra efforts for system verification.|
|| http://www.cadence.com/eu/Documents/MicrosoftPowerPoint ToT2013openend.pdf |
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