博碩士論文 106521109 詳細資訊




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姓名 陳昶亨(Chang-Heng Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 C/X頻段低功耗寬頻接收機前端暨氮化鎵X頻段升頻式混頻器之研製
(Implementations on C/X-band Low Power Wideband Receiver Front-end and X-band GaN Up-conversion Mixer)
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摘要(中) 本篇論文分別利用tsmcTM 180 nm CMOS和穩懋半導體III-V族WINTM GaN 0.25 µm製程設計,論文中總共4顆晶片,其中CMOS部分為C/X頻段寬頻低雜訊放大器與接收機之研製,III-V族WINTM GaN 0.25µm製程為X頻段升頻式混頻器之研製。本篇論文研究主題主要為利用變壓器改善CMOS製程缺點所造成的轉導能力(gm)不足,藉此來對寬頻接收機進行最佳化設計與應用於海事雷達發射機中升頻式混頻器的隔離度問題改善。
第一顆寛頻低雜訊放大器係利用閘極與汲極變壓器實現輸入寬頻響應和前一級源極與本身汲極變壓器來拓展頻寬,並推導變壓器耦合對電感關係式,藉此改善高頻轉導值,實現寬頻低雜訊放大器的應用,使其應用於C/X頻段。量測結果顯示最高增益(|S21|)為15.6 dB,3-dB頻寬為5.1 – 11.5 GHz,最低雜訊為4.43 dB,線性度P1dB為 -10 ~ -13 dBm,IIP3為0 ~ -5 dBm,功耗為12.5 mW。
第二顆電路為C/X頻段低功耗寬頻接收機前端,第一級為寬頻低雜訊放大器,因為考慮到接收機的佈局問題,所以對第一顆寬頻低雜訊放大器佈局進行修改,之後考慮各個子電路間的阻抗相對關係,分析電流模態與電壓模態操作。整體接收機前端子電路分別為寬頻低雜訊放大器,第二級為寬頻巴倫是利用共振點來產生頻寬的架構,第三級為混頻器採用雙平衡式架構,最後為轉阻放大器(Trans-impedance Amplifier, TIA),採用差動放大器的架構,本次設計兩級的轉阻放大器,通道頻寬則由RC回授來決定。量測結果顯示最高轉換增益(Conversion Gain)為31.5 dB, 3-dB頻寬為4.8 – 11 GHz,LO到RF隔離度大於70 dB,LO到IF隔離度大於45 dB,IF頻寬為125 MHz。線性度P1dB為-25 ~ -32 dBm與IIP3為-23.5 ~ -32.5 dBm,整體功耗為21.9 mW。
第三顆為GaN 0.25 µm製程的X頻段升頻式混頻器,為一個單平衡式架構的X頻段升頻式混頻器,並在本地震盪源與射頻輸出端接上馬遜巴倫,方便之後系統上的整合。量測結果顯示最高轉換損耗(Conversion Loss)為8.5 dB, 3-dB頻寬為8.5 – 10.8 GHz,LO到RF隔離度大於12.4 dB,輸出功率8.1 dBm,IF頻寬為1.1 GHz。線性度P1dB為12 ~ 22 dBm,整體功耗為0 mW。
第四顆為GaN 0.25µm製程的X頻段升頻式混頻器,但是為了改善第三顆的本地震盪源到射頻端隔離度的問題,在架構上為一個單端的升頻式混頻器加上倍頻器,先利用混頻器將頻率提升至5 GHz,接著利用倍頻器將頻率提升至計畫所需頻率。在基頻頻率上也將頻率改為150 MHz來進行改善本地震盪源頻率與射頻頻率的距離,此外在倍頻器輸出端還接上5 GHz傳輸線開路,使5 GHz訊號看到高阻來改善隔離度。模擬結果顯示最高轉換損耗(Conversion Loss)為4 dB, 3-dB頻寬為9.2 – 11.2 GHz,LO到RF隔離度大於33.5 dB,輸出功率4.1 dBm,IF頻寬為240MHz。整體功耗為630 mW。
摘要(英) This thesis presents CMOS wideband low noise amplifier (LNA) and receiver (Rx) front-end in tsmcTM 180 nm CMOS technology and X-band mixers in WINTM 0.25 μm GaN/SiC technology. Four chips including C/X bnad wideband LNA, receiver, and two GaN up-conversion mixers were successfully designed, fabricated and verified. The main research topic is to design a wideband receiver using transformer feedback technique to overcome the limitation of low transconductance of (gm) in CMOS process. Meanwhile, the author developed the methodology to improve the isolation of up-converter mixer in radar transmitter.
The bandwidth extension technique applied in LNA was developed by source-drain transformer coupled between the first and second stages. The formula of the transformer with its self-inductance and coupling factor were derived and implemented in LNA. The measurement results show that the LNA achieved a maximum gain (S21) of 15.6 dB, a 3-dB bandwidth of 5.1 – 11.5 GHz, a lowest noise figure of 4.43 dB, a P1dB of -10 ~ -13 dBm and an IIP3 of 0 ~ - 5 dBm, power consumption of 12.5 mW.
The second circuit is a C/X band wideband low-power receiver front end. The receiver consists of a wideband LNA, a wideband balun, a double balanced mixer and a two-stage transimpedance amplifier (TIA). The channel bandwidth is determined by the RC feedback in TIA. The measurement results show the receiver achieved a maximum conversion gain of 31.5 dB, a 3-dB bandwidth of 4.8 – 11 GHz, an LO-to- RF isolation greater than 70 dB, an LO-to-IF isolation greater than 45 dB, and an IF bandwidth of 125 MHz. The P1dB is -25 ~ -32 dBm and the IIP3 is -23.5 ~ -32.5 dBm, power consumption of 21.9 mW, respectively.
The third circuit is an X-band GaN single-balanced (SBM) resistive up-mixer. Two lumped-element Marchand baluns are used in the LO and RF ports for convenient testing and further integration. The measurement results presents a minimum conversion loss of 8.5 dB, a 3-dB bandwidth of 8.5 - 10.8 GHz, an LO to RF isolation of greater than 12.4 dB, an output power of 8.1 dBm, and an IF bandwidth of 1.1 GHz. The P1dB is 12 ~ 22 dBm, power consumption of 0 mW, respectively. The fourth circuit is an X-band GaN up-mixer which adopted a single-ended up-converter mixer cascading a frequency doubler to overcome the isolation problem in conventional SBM. A 5 GHz quarter-wavelength open stub is added in the output of doubler to increase the LO-to-RF isolation. Meanwhile, IF frequency is selected high up to 150 MHz to relax the specification of filter design. The simulations show the receiver achieved a maximum conversion Loss of 4 dB, a 3-dB bandwidth of 9.2 – 11.2 GHz, an LO-to- RF isolation greater than 33.5 dB, and an IF bandwidth of 240 MHz, power consumption of 630 mW, respectively.
關鍵字(中) ★ 低功耗
★ C/X頻段
★ 接收機前端
★ 氮化鎵
★ 升頻式混頻器
關鍵字(英) ★ Low Power
★ C/X-band
★ Receiver Front-end
★ GaN
★ Up-conversion Mixer
論文目次 目錄

摘要 I
Abstract III
誌謝 V
目錄 VII
圖目錄 VIII
表目錄 XII
第一章 緒論 1
1-1 研究現況 1
1-2 研究成果 1
1-3 章節簡介 2
第二章 應用於C/X頻段之寬頻低雜訊放大器 4
2-1 研究動機 4
2-2 電路設計與分析 6
2-3 電路模擬與量測結果 23
2-4 結果與討論 31
第三章 應用於C/X頻段低功耗寬頻接收機前端 33
3-1 研究動機 33
3-2 電路架構與設計 34
3-3 電路模擬與量測結果 54
3-4 結果與討論 64
第四章 應用於X頻段升頻式混頻器 66
4-1 研究動機 66
4-2 電路架構與設計 67
4-3 電路模擬與量測結果 71
4-4 結果與討論 79
第五章 應用於倍頻器於X頻段升頻式混頻器 81
5-1 研究動機 81
5-2 電路架構與設計 82
5-3 電路模擬結果 96
第六章 結論 104
6-1 電路總結 104
6-2 未來方向 106
參考文獻 107
參考文獻 [1] K. Chien and H. Chiou, "A 0.6–6.2 GHz wideband LNA using resistive feedback and gate inductive peaking techniques for multiple standards application," in 2013 Asia-Pacific Microwave Conference Proceedings (APMC), 2013, pp. 688-690.
[2] O. A. Hidayov, N. H. Nam, G. Yoon, S. K. Han, and S. G. Lee, "0.7-2.7 GHz wideband CMOS low-noise amplifier for LTE application," Electronics Letters, vol. 49, no. 23, pp. 1433-1435, 2013.
[3] Y. Lin, C. Wang, G. Lee, and C. Chen, "High-Performance Wideband Low-Noise Amplifier Using Enhanced π-Match Input Network," IEEE Microwave and Wireless Components Letters, vol. 24, no. 3, pp. 200-202, 2014.
[4] N. Li, W. Feng, and X. Li, "A CMOS 3–12-GHz Ultrawideband Low Noise Amplifier by Dual-Resonance Network," IEEE Microwave and Wireless Components Letters, vol. 27, no. 4, pp. 383-385, 2017.
[5] Y. Yu, H. Liu, Y. Wu, and K. Kang, "A 54.4–90 GHz Low-Noise Amplifier in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2892-2904, 2017.
[6] P. Chang and S. S. H. Hsu, "A Compact 0.1–14-GHz Ultra-Wideband Low-Noise Amplifier in 0.13-µm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 10, pp. 2575-2581, 2010.
[7] B. Guo and X. Li, "A 1.6–9.7 GHz CMOS LNA Linearized by Post Distortion Technique," IEEE Microwave and Wireless Components Letters, vol. 23, no. 11, pp. 608-610, 2013.
[8] M. A. Roein, "Design and analysis of a 3.1–10.6 GHz UWB low noise amplifier with current reused technique," in 2019 5th Conference on Knowledge Based Engineering and Innovation (KBEI), 2019, pp. 030-035.
[9] Yo-Sheng Lin , Jin-Fa Chang, and Shey-Shi Lu, “Analysis and design of CMOS distributed amplifier using inductively peaking cascaded gain cell for UWB systems, ”IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, Oct. 2011.
[10] A. Mineyama, Y. Kawano, M. Sato, T. Suzuki, N. Hara, and K. Joshin, "A millimeter-wave CMOS low noise amplifier using transformer neutralization techniques," in Asia-Pacific Microwave Conference 2011, 2011, pp. 223-226.
[11] J. Tsai, W. Huang, C. Lin, and R. Chang, "An X-band low-power CMOS low noise amplifier with transformer inter-stage matching networks," in 2014 9th European Microwave Integrated Circuit Conference, 2014, pp. 524-527.
[12] H. Tsai, H. Pan, H. Chen, and J. Y. Liu, "A W-Band Low-Noise Amplifier with Shunt Inductors and Transformer Feedback Gm-Boosting Techniques," in 2018 Asia-Pacific Microwave Conference (APMC), 2018, pp. 657-659.
[13] T. Yao et al., "Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio," IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1044-1057, 2007.
[14] J. Chang and Y. Lin, "3.15 dB NF, 7.2 mW 3–9 GHz CMOS ultra-wideband receiver front-end," Electronics Letters, vol. 47, no. 25, pp. 1401-1402, 2011.
[15] C. Li, C. Kuo, and M. Kuo, "A 1.2-V 5.2-mW 20–30-GHz Wideband Receiver Front-End in 0.18-µm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 11, pp. 3502-3512, 2012.
[16] J. Kim and J. Silva-Martinez, "Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications," IEEE Journal of Solid-State Circuits, vol. 48, no. 9, pp. 2090-2103, 2013.
[17] A. W. L. Ng, S. Y. Zheng, H. Leung, Y. Chao, and H. C. Luong, "A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio," in 2013 Proceedings of the ESSCIRC (ESSCIRC), 2013, pp. 181-184.
[18] R. Ye, T. Horng, and J. Wu, "Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices," IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 5, pp. 1229-1238, 2014.
[19] A. Homayoun and B. Razavi, "A Low-Power CMOS Receiver for 5 GHz WLAN," IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 630-643, 2015.
[20] K. Kwon, J. Han, and I. Nam, "A Wideband Receiver Front-End Employing New Fine RF Gain Control Driven by Frequency-Translated Impedance Property," IEEE Microwave and Wireless Components Letters, vol. 25, no. 4, pp. 247-249, 2015.
[21] H. Wu, N. Wang, Y. Du, and M. F. Chang, "A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 3, pp. 1053-1062, 2015.
[22] T. Heller, E. Cohen, and E. Socher, "A 102–129-GHz 39-dB Gain 8.4-dB Noise Figure I/Q Receiver Frontend in 28-nm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 5, pp. 1535-1543, 2016.
[23] Y. Ping-Chun, L. Wei-Cheng, and C. Hwann-Kaeo, "Compact 28-GHz subharmonically pumped resistive mixer MMIC using a lumped-element high-pass/band-pass balun," IEEE Microwave and Wireless Components Letters, vol. 15, no. 2, pp. 62-64, 2005.
[24] T. Wu and C. Meng, "10-GHz Highly Symmetrical Sub-Harmonic Gilbert Mixer Using GaInP/GaAs HBT Technology," IEEE Microwave and Wireless Components Letters, vol. 17, no. 5, pp. 370-372, 2007.
[25] D. Y. Jung and C. S. Park, "A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 µm CMOS," IEEE Microwave and Wireless Components Letters, vol. 18, no. 8, pp. 551-553, 2008.
[26] J. Tsai, H. Yang, T. Huang, and H. Wang, "A 30–100 GHz Wideband Sub-Harmonic Active Mixer in 90 nm CMOS Technology," IEEE Microwave and Wireless Components Letters, vol. 18, no. 8, pp. 554-556, 2008.
[27] H. Wei, C. Meng, P. Wu, and K. Tsung, "K-Band CMOS Sub-Harmonic Resistive Mixer With a Miniature Marchand Balun on Lossy Silicon Substrate," IEEE Microwave and Wireless Components Letters, vol. 18, no. 1, pp. 40-42, 2008.
[28] J. Oh, S. Moon, D. S. Kang, and S. Kim, "High-Performance 94-GHz Single-Balanced Diode Mixer Using Disk-Shaped GaAs Schottky Diodes," IEEE Electron Device Letters, vol. 30, no. 3, pp. 206-208, 2009.
[29] J. Chen and H. Wang, "A High Gain, High Power K-Band Frequency Doubler in 0.18µm CMOS Process," IEEE Microwave and Wireless Components Letters, vol. 20, no. 9, pp. 522-524, 2010.
[30] C. Xu, X. Feng, H. Ru, and W. Xin′an, "Design of radar single-balance mixer for intelligent transportation," in 2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2012, vol. 5, pp. 1-4.
[31] C. Yeh et al., "A 3.5 GHz antiparallel diode pair mixer in GaN-on-Si HEMT technology," in 2012 4th International High Speed Intelligent Communication Forum, 2012, pp. 1-4.
[32] O. Habibpour, J. Vukusic, and J. Stake, "A 30-GHz Integrated Subharmonic Mixer Based on a Multichannel Graphene FET," IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 2, pp. 841-847, 2013.
[33] M. v. Heijningen, J. A. Hoogland, A. P. d. Hek, and F. E. v. Vliet, "6–12 GHz double-balanced image-reject mixer MMIC in 0.25μm AlGaN/GaN technology," in 2014 9th European Microwave Integrated Circuit Conference, 2014, pp. 65-68.
[34] H. Chiou, Y. Chen, and H. Yen, "A 5–12 GHz double-balanced power mixer with differential transmission-line transformer in 0.18 μm CMOS," in 2017 IEEE CPMT Symposium Japan (ICSJ), 2017, pp. 25-28.
[35] T. T. Nguyen, K. Fujii, and A. Pham, "Highly Linear Distributed Mixer in 0.25- µm Enhancement-Mode GaAs pHEMT Technology," IEEE Microwave and Wireless Components Letters, vol. 27, no. 12, pp. 1116-1118, 2017.
[36] M. Y. Algumaei, N. A. Shairi, Z. Zakaria, and B. H. Ahmad, "A Single Balanced Mixer Using Compact Branch Line Balun for Ultra-Wideband Applications," in 2018 IEEE International Workshop on Electromagnetics:Applications and Student Innovation Competition (iWEM), 2018, pp. 1-2.
[37] S. Pegwal, M. P. Abegaonkar, A. Basu, and S. K. Koul, "Single Balanced Mixer for UWB Applications," in 2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2018, pp. 1-3.
[38] 陳品豪, "低功耗I/Q寬頻接收機前端電路應用於C/X頻帶," 碩士, 電機工程學系, 國立中央大學, 桃園縣, 2017.
[39] 徐冠忠, "應用於C/X頻段之互補式金氧半導體低功耗寬頻接收機前端電路暨X頻段氮化鎵發射機之研製," 碩士, 電機工程學系, 國立中央大學, 桃園縣, 2018.
[40] 傅奕文, "應用變壓器耦合與負偏壓技術於Ka頻段單刀雙擲開關器暨應用電容共振技術於X/Ka頻段III-V族開關器之研製," 碩士, 電機工程學系, 國立中央大學, 桃園縣, 2018.
指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2019-8-20
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