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姓名	蘇正瑋(Cheng-Wei Su)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	考慮後段製程連線及佈局優化之積層型三維靜態隨機存取記憶體 (Multi-tier Monolithic 3D SRAM Considering BEOL Interconnect and Layout Optimization)
相關論文	★ 積層型三維邏輯電路之性能分析 ★ 無接面鐵電場效電晶體與量測模式對增強極化之影響
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摘要(中)	隨著製程技術的演進、EUV(Extreme ultraviolet lithography)的引進，使電晶體可以進一步微縮，並讓晶片上可以容納更多的電晶體，與此同時，內部繞線(Interconnect)的結構也勢必變小，因此增加了後段製程(BEOL)的金屬電阻值，這樣的情況會使電路的特性變差。因此，本論文利用積層型三維(Monolithic 3D)堆疊技術，設計三維的靜態隨機存取記憶體(Static Random Access Memory, SRAM)電路佈局來改善其特性。 本論文主要探討的電路是SRAM，利用TCAD的Mixed-Mode及內部導線模型(π-3 Model)來分析SRAM的電路特性。論文內容分為三個主題，第一部分會探討先進技術節點下內部導線的微縮對SRAM電路所產生的影響，研究結果顯示內部導線電阻值的增加會延長傳輸訊號的時間使SRAM電路特性有顯著的退化。第二部分，我們利用Transistor-Level積層型三維堆疊來設計SRAM，Transistor-Level積層型三維堆疊是將P型跟N型電晶體製作在不同的平面上，可以調整製作流程並獨立優化電晶體特性，不但能縮小SRAM的單元(cell)面積也能減少內部導線的繞線長度，使字元線及位元線的電阻電容值降低，考慮在一/二/三層的積層型三維SRAM的佈局下，分析SRAM cell的讀取存取時間(Read access time)、寫入時間(Time-to-write)、動態能量消耗及能量延遲積。 第三部分，我們探討未來具有潛力的通道材料—二維材料，分析不同閘極位置的二氧化鉬場效電晶體及積層型三維堆疊的6T SRAM佈局優化，再比較由背閘極式場效電晶體組成的積層型三維SRAM的特性，由分析結果可得知三層積層型三維SRAM與一層相比可以改善28.4%讀取存取時間、21.3%動態能量及43.6%能量延遲積，並增強寫入的穩定度。本篇論文提出的高能量效率背閘極式三層積層型三維SRAM，具有更好的潛力應用在邊緣運算裝置中。
摘要(英)	With the evolution of process technology and the introduction of EUV, transistors can be scaled down and more transistors can be accommodated on the wafer. Continued scaling of the transistor and metal interconnection geometry is accompanied by the increased wire routing resistance which degrades the circuit performance. Therefore, the thesis uses monolithic 3D stacking technology to design a three-dimension SRAM circuit layout to improve SRAM characteristics. The thesis mainly explores static random access memory, we analyze SRAM performance by using TCAD coupled with the interconnect π-3 model. In the first part, we discuss the impact of scaled interconnect metal on SRAM circuits in advanced technology nodes. The research results show that increased back-end of line metal resistance prolongs the signal transmission time and degrades SRAM performance significantly. In the second part, we design SRAM with transistor-level monolithic 3D integration. In transistor-level M3D design, p-type and n-type transistors are fabricated on different layers. Thus, PMOS and NMOS devices can be optimized separately. It can reduce not only the SRAM cell area, but also interconnect lengths that makes wire routing resistance and capacitance low. And we analyze the cell area, read access time, time-to-write, and energy efficiency in 1-tier, 2-tier, and 3-tier monolithic 3D SRAM cell. In the third part, we discuss potential channel materials—2D material and comprehensively analyze gate topology of MoS2 FETs, and the layout optimization of multi-tier 6T SRAM cells. Compared to the multi-tier back-gated(BG) SRAM cell designs, the monolithic 3-tier BG SRAM cell shows 28.4% read access time, 21.3% dynamic energy, and 43.6% energy-delay product improvements over 1-tier BG SRAM and enhance the write stability. The energy- and area-efficient 3-tier BG SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices.
關鍵字(中)	★ 積層型三維堆疊 ★ 二維材料 ★ 後段製程 ★ 靜態隨機存取記憶體 ★ 能量效率	關鍵字(英)	★ Monolithic 3D integration ★ 2D material ★ back-end-of-the-line (BEOL) ★ SRAM ★ energy efficiency
論文目次	摘要 I Abstract III 致謝 V 目錄 VI 圖目錄 IX 表目錄 XIV 第一章 導論 1 1.1 背景與相關研究 1 1.1.1 內部導線 4 1.1.2 積層型三維結構 (Monolithic 3D) 6 1.1.3 二維材料 8 1.2 研究動機 11 1.3 論文架構 13 第二章 內部導線電阻電容值對靜態隨機存取記憶體之影響 14 2.1 前言 14 2.2 6T 靜態隨機存取記憶體介紹 15 2.3 內部導線模型(Interconnect model) 17 2.4 元件結構與模擬參數 21 2.5 靜態隨機存取記憶體單元性能分析 23 2.5.1 記憶體讀取存取時間分析 27 2.5.2 記憶體寫入時間分析 33 2.6 靜態雜訊邊界(Static Noise Margin) 35 2.7 結論 39 第三章 分析積層型三維靜態隨機存取記憶體 40 3.1 前言 40 3.2 元件結構與模擬參數 41 3.3 佈局中內部導線的電阻電容 42 3.4 比較傳統靜態隨機記憶體與積層型三維堆疊靜態隨機存取記憶體 43 3.4.1 單元面積(Cell area) 43 3.4.2 記憶體讀取存取時間及寫入時間分析 45 3.5 WSNM改善 51 3.6 動態能量消耗與能量延遲積的比較 52 3.7 結論 54 第四章 二維材料場效電晶體應用於積層型三維靜態隨機存取記憶體 55 4.1 前言 55 4.2 元件結構與相關參數 56 4.3 佈局設計 59 4.4 背閘極式靜態記憶體特性分析 61 4.4.1 靜態雜訊邊界 61 4.4.2 一層與三層背閘極式靜態隨機存取記憶體性能分析 62 4.4.3 WSNM及能量的改善 65 4.5 結論 66 第五章 總結 67 參考文獻 69
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指導教授	胡璧合 李依珊(Vita Pi-Ho Hu Yi-Shan Lee)	審核日期	2021-1-20
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