運用粒子群最佳化演算法之自適應等化器與時序恢復電路設計

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姓名

蔡忠穎(Chung-Ying Tsai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

運用粒子群最佳化演算法之自適應等化器與時序恢復電路設計
(Design of Adaptive Equalizer and Timing Recovery Circuit with Particle Swarm Optimization Algorithm)

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至系統瀏覽論文 (2026-8-31以後開放)

摘要(中)

本論文依據IEEE 802.3bz™-2016規範標準[1]，設計出乙太網路傳輸之數位基頻收發機晶片來送收PAM-16編碼之訊號。有線乙太網路通道屬於緩慢時變通道，因此提出通道等化器演算法、時序恢復電路及數位電路設計，在演算法的選擇上使用較低複雜度的LMS演算法來解決通道效應。其中通道等化器採用前饋等化器（Feedforward Equalizer, FFE）、決策回饋等化器（Decision Feedback Equalizer, DFE）、湯林森-何洛緒瑪預編碼（Tomlinson-Harashima Precoder , THP）[2][3]以及輔助回授等化器（Auxiliary Feedback Equalizer, AFBE）[4]做設計。為解決時脈不匹配效應以及通道的角度偏移效應，以鎖相迴路設計之時序恢復電路（Timing Recovery）採用穆勒與姆勒演算法（Mueller and Muller, M&M）的相位檢測方法實現，並透過粒子群最佳化演算法（Particle Swarm Optimization Algorithm, PSO）[5]來選擇通道偏移的角度，其目的在找到較好的通道角度以提升其效能。在硬體實現上，先利用Verilog HDL撰寫，透過SMIMS VeriEnterprise Xilinx FPGA進行即時驗證電路功能，且經由Design Compiler來驗證在製程選擇為TSMC 40 nm下的電路功能，最後也使用相同製程來實現晶片。

摘要(英)

This work designs the digital baseband transceiver for Ethernet transmission using PAM-16 signal based on standard IEEE 802.3bz™-2016. The wired Ethernet cables are slow time-varying channels while high speed signals transmitted. Thus, the channel equalizer, timing recovery circuit and the related digital circuit design are proposed to solve the channel effect with lower complexity LMS algorithm. The channel equalizer adopts the feedforward equalizer, decision feedback equalizer, Tomlinson-Harashima Precoder and auxiliary feedback equalizer. In order to solve the clock mismatch effect and the channel angle offset effect, the Timing Recovery circuit designed with a phase-locked loop is implemented using the Mueller and Muller algorithm. Furthermore, the Particle Swarm Optimization Algorithm (PSO) is used to select the channel offset in purpose to find a better channel angle to increase its effectiveness.
At last, this hardware design is coded in Verilog HDL and simulated. The circuit function is verified in real time through SMIMS VeriEnterprise Xilinx FPGA, and implemented under TSMC 40nm process through Design Compiler, and finally use the same process to complete the chip.

關鍵字(中)

★ 等化器
★ 時序恢復

關鍵字(英)

★ Equalizer
★ Timing Recovery

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 x
第一章緒論 - 1 -
1.1背景 - 1 -
1.2研究動機 - 1 -
1.3論文貢獻 - 2 -
1.4論文架構 - 2 -
第二章等化器架構介紹 - 3 -
2.1 濾波器架構 - 3 -
2.2 線性等化器（LE） - 5 -
2.3 可適性等化器（AE） - 6 -
2.4 決策回授等化器（DFE） - 6 -
2.6 輔助回授等化器（AFBE） - 10 -
第三章等化器演算法介紹 - 11 -
3.1 非盲目等化器演算法 - 11 -
3.1.1 最小均根（Least Mean Square, LMS） - 11 -
3.2 盲目等化器演算法 - 14 -
3.2.1 決策導向（DD）演算法 - 14 -
3.2.2 定值模數演算法（CMA） - 16 -
3.2.3 粒子群最佳化演算法（PSO） - 18 -
3.2.4 具有微分擾動速度的粒子群最佳化演算法（PSO-DV） - 21 -
第四章時序恢復電路介紹 - 23 -
4.1 基本介紹 - 23 -
4.2時序恢復電路系統概要 - 24 -
4.2.1 相位檢測器（PD） - 25 -
4.2.2 迴路濾波器（LF） - 27 -
4.2.3 壓控振盪器（VCO） - 28 -
第五章系統架構與模擬結果 - 29 -
5.1 系統架構 - 29 -
5.2 系統環境 - 31 -
5.3 模擬環境 - 33 -
5.3.1 十公尺模擬環境 - 33 -
5.3.2 五十公尺模擬環境 - 33 -
5.3.2 一百公尺模擬環境 - 34 -
5.4 等化器模擬結果 - 34 -
5.4.1 CMA/DD演算法模擬結果 - 35 -
5.4.2 PSO演算法模擬結果 - 36 -
5.4.3 PSO-DV演算法模擬結果 - 37 -
5.4.3 輔助回授等化器模擬結果 - 38 -
5.5 時序恢復電路架構 - 38 -
5.5.1 十公尺模擬環境時序恢復電路模擬結果 - 50 -
5.5.2 五十公尺模擬環境時序恢復電路模擬結果 - 51 -
5.5.3 一百公尺模擬環境時序恢復電路模擬結果 - 52 -
5.5 系統驗證 - 53 -
第六章電路架構與晶片實現 - 54 -
6.1硬體設計規格 - 54 -
6.2 電路設計流程 - 55 -
6.3硬體電路介紹 - 56 -
6.3.1等化器電路 - 56 -
6.3.2粒子群最佳化演算法電路 - 58 -
6.3.3時序恢復電路 - 59 -
6.4模擬驗證 - 60 -
6.5晶片設計結果 - 63 -
第七章結論與未來展望 - 69 -
參考文獻 - 70 -

參考文獻

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指導教授

薛木添

審核日期

2021-9-16

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