| 摘要(英) |
There are quite a few notable applications in Ka band, such as the fifth-generation (5G) mobile communications at 28 GHz and 39 GHz and the cloud radar at 35 GHz. In both 5G communication and radar applications, phased arrays play important roles. Phase shifters are indispensable components in a phased array. In this thesis, 35-GHz 4-bit and 5-bit digital phase shifters are designed by adopting transmission-line-based all-pass network topology and implemented using TSMC 0.18-μm CMOS process. Moreover, cross-coupled pairs are incorporated in the phase shifter design to provide negative transconductance and thereby compensate the loss resulting from the passive components.
In Chapter 2, transmission-line-based all-pass network is introduced and its design equations are derived. Next, the equivalent circuit for complementary cross-coupled pair is introduced. Finally, simulations are performed to verify that, by incorporating cross-coupled pair, the insertion loss of the all-pass phase shifter could indeed be lowered.
In Chapter 3, a 4-bit phase shifter is designed using the aforementioned transmission-line-based all-pass network with loss compensation. The 22.5°, 45°, and 90° phase-shifting stages assume the topology of fully-differential transmission-line-based all-pass network, whereas 180° phase-shifting stage is realized by a pair of SPDT switches. The chip area is 1×2 mm2. Simulation results show that, between 26.7 GHz and 38.8 GHz (36.9% bandwidth), the RMS phase error is less than 2°, the amplitude error is within ±1 dB, and the insertion loss is less than 11.7 dB. However, measurement results show that, for all 16 states, the phase shifts are larger than expected, causing the RMS phase error to deteriorate to 22.5°, and the insertion loss is only less than 24.8 dB within Ka band, which differs a lot from the simulation results. In this design, the cross-coupled pairs in the circuits should consume constant amount of DC current regardless of the phase-shifting states. However, during measurement, it is found that there is DC current flowing through the cross-coupled pair only when the phase shifting stage is in on state. In other words, the cross-coupled pairs did not function correctly, which may be one possible reason why the insertion loss increases so much. Moreover, after re-simulation, it is found that there may be additional parasitic capacitance in parallel with the cross-coupled pair, which is responsible for the increase of phase errors.
In Chapter 4, a 5-bit phase shifter is designed by adopting the same transmission-line-based all-pass network topology with the same design procedure, except that lower system impedance and characteristic impedance are used, hoping that the loss of the transmission lines may be lower. Simulation results show that, between 33.0 GHz and 39.4 GHz (17.7% bandwidth), the RMS phase error is less than 3°, the amplitude error is within ±0.85 dB, and the insertion loss is less than 14.1 dB. However, measurement results show that the phase shifts deviate a lot, leading to a deteriorated RMS phase error of 102.5°, and the insertion loss is only less than 56.0 dB within Ka band. During measurement, it is also found that the cross-coupled pairs in this circuit did not function correctly, either. After re-simulation, the simulated results could fit the measured results at low frequencies by adding parasitic components to the cross-coupled pairs. But unfortunately, actual cause for the large discrepancy between the simulated and measured results has yet to be found.
In this thesis, fully-differential digital phase shifters are successfully designed using transmission-line-based all-pass network with loss compensation. However, large discrepancies between the measured and simulated results are observed. Nonetheless, after re-simulations, part of the reasons for the large discrepancy has been proposed. |
| 參考文獻 |
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