參考文獻 |
[1] I.R. Committee, "International Roadmap for Devices and Systems," 2020 Edition. More Moore white paper.
[2] J. S. Meena, S. M. Sze, U. Chand and T.-Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale Res Lett 9, 526 (2014),
https://doi.org/10.1186/1556-276X-9-526.
[3] J. Wu et al., "Adaptive Circuit Approaches to Low-Power Multi Level/Cell FeFET Memory," 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, 2020, pp. 407-413.
[4] D. Reis et al., "Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 5, no. 2,
pp. 103-112, Dec. 2019, doi: 10.1109/JXCDC.2019.2930284.
[5] J. Hung, X. Li, J. Wu and M. Chang, "Challenges and Trends in Developing Nonvolatile Memory-Enabled Computing Chips for Intelligent Edge Devices," IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1444-1453, April 2020.
[6] K. Tang et al., "Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices," 2019 Symposium on VLSI Technology, Kyoto, 2019, pp. T166-T167.
[7] Sentaurus TCAD, O-2018-6 Manual.
[8] V. P. Hu et al., "Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Nonvolatile Memory and Neuromorphic Applications," 2019 Symposium on VLSI Technology, Kyoto, Japan, 2019, pp. T134-T135, doi: 10.23919/VLSIT.2019.8776555.
[9] J. Valasek, "Piezo-Electric and Allied Phenomena in Rochelle Salt," Physical Review, vol. 17, pp. 475, 1921.
[10] M. H. Park et al., "A comprehensive study on the structural evolution of HfO2 thin films doped with various dopants, " J. Mater. Chem. C, vol. 5, no. 19, pp. 4677–4690, 2017
[11] J. Müller et al., "Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG," 2012 Symposium on VLSI Technology (VLSIT), Honolulu, Hl, 2012, pp. 25-26.
[12] T. S. Böscke et al., "Ferroelectricity in hafnium oxide thin films," in Applied Physics Letters, vol. 99, no. 10, p. 102903, May 2011.
[13] S. Dünkel et al., "A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 19.7.1-19.7.4, doi: 10.1109/IEDM.2017.8268425.
[14] K.-Y. Hsiang et al., "Ferroelectric HfZrO2 With Electrode Engineering and Stimulation Schemes as Symmetric Analog Synaptic Weight Element for Deep Neural Network Training," in IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4201-4207, Oct. 2020, doi:10.1109/TED.2020.3017463.
[15] Y. -W. Lee and V. P. -H. Hu, "Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180661.
[16] K. Ni et al., "A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 131-132, doi: 10.1109/VLSIT.2018.8510622.
[17] Bo Jiang, Zurcher, Jones, Gillespie and Lee, "Computationally Efficient Ferroelectric Capacitor Model For Circuit Simulation," 1997 Symposium on VLSI Technology, 1997, pp. 141-142, doi: 10.1109/VLSIT.1997.623738.
[18] Hang-Ting Lue, Chien-Jang Wu and Tseung-Yuen Tseng, "Device modeling of ferroelectric memory field-effect transistor (FeMFET)," in IEEE Transactions on Electron Devices, vol. 49, no. 10, pp. 1790-1798, Oct. 2002,
doi: 10.1109/TED.2002.803626.
[19] F. Mo et al., "Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention Model," 2021 Symposium on VLSI Technology, 2021, pp. 1-2.
[20] J. Chow, A. Sheikholeslami, J. S. Cross and S. Masui, "A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits," 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04Co37525), 2004, pp. 448-449, doi: 10.1109/VLSIC.2004.1346646.
[21] C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi, "On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 368-374, 2019, doi: 10.1109/JEDS.2019.2899727.
[22] K. Ni et al., "Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance," in IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2461-2469, June 2018, doi: 10.1109/ TED.2018.2829122.
[23] A. Mallick and N. Shukla, "Evaluation of Bulk and SOI FeFET Architecture for Nonvolatile Memory Applications," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 425-429, 2019, doi: 10.1109/JEDS .2019.2906834.
[24] F. -C. Wu, W. -X. You and P. Su, "Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation," 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, pp. 78-79, doi: 10.1109/VLSI-TSA48913.2020.9203737.
[25] K. Ni et al., "SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications," 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 13.2.1-13.2.4, doi: 10.1109/ IEDM. 2018.8614496.
[26] Kazemi, A., Rajaei, R., Ni, K., Datta, S., Niemier, M., & Hu, X.S. (2020). A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference. 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5.
[27] M. -H. Yan et al., "BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 4.6.1-4.6.4, doi: 10.1109/IEDM13553.2020.9371916.
[28] U. Schroeder et al., "Impact of field cycling on HfO2 based nonvolatile memory devices," 2016 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, 2016, pp. 364-368.
[29] Xiao, Wenwu et al. “Memory Window and Endurance Improvement of Hf0.5Zr0.5O2-Based FeFETs with ZrO2 Seed Layers Characterized by Fast Voltage Pulse Measurements.” Nanoscale research letters, vol. 14,1 254. 26 Jul. 2019, doi:10.1186/s11671-019-3063-2
[30] D. Reis, M. T. Niemier and X. S. Hu, "A Computing-in-Memory Engine for Searching on Homomorphically Encrypted Data," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 5, no. 2, pp. 123-131, Dec. 2019, doi: 10.1109/JXCDC.2019.2931889.
[31] P. Wang et al., "Investigating Ferroelectric Minor Loop Dynamics and History Effect—Part II: Physical Modeling and Impact on Neural Network Training," in IEEE Transactions on Electron Devices, vol. 67, no. 9, pp. 3598-3604, Sept. 2020, doi: 10.1109/TED.2020.3009956.
[32] B. -K. Huang, W. -X. You and P. Su, "Comparison of 2-T FeFET Nonvolatile Memory Cells: Gate Select vs. Drain Select," 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1-2, doi: 10.1109/VLSI-TSA51926.2021.9440073.
[33] J. Wu, H. Zhong, K. Ni, Y. Liu, H. Yang and X. Li, "A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs," 2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, pp. 1-6.
[34] X. Li et al., "Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs," in IEEE Design & Test, vol. 36, no. 3, pp. 39-45, June 2019, doi: 10.1109/MDAT.2019.2902094.
[35] S. Slesazeck et al., "Uniting The Trinity of Ferroelectric HfO2 Memory Devices in a Single Memory Cell," 2019 IEEE 11th International Memory Workshop (IMW), 2019, pp. 1-4, doi: 10.1109/IMW.2019.8739742.
[36] X. Sun, P. Wang, K. Ni, S. Datta and S. Yu, "Exploiting Hybrid Precision for Training and Inference: A 2T-1FeFET Based Analog Synaptic Weight Cell," 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 3.1.1-3.1.4, doi: 10.1109/IEDM.2018.8614611.
[37] B. Obradovic et al., "A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 438-448, 2018, doi: 10.1109/JEDS.2018.2817628.
[38] M. Jerry et al., "Ferroelectric FET analog synapse for acceleration of deep neural network training," 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 6.2.1-6.2.4, doi: 10.1109/IEDM.2017.8268338.
[39] K. Ni et al., "In-Memory Computing Primitive for Sensor Data Fusion in 28 nm HKMG FeFET Technology," 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 16.1.1-16.1.4, doi: 10.1109/IEDM.2018. 8614527.
[40] K. Ni, S. Dutta and S. Datta, "Ferroelectrics: From Memory to Computing," 2020 25th Asia and South Pacific Design Automation Conference (ASPDAC), 2020, pp. 401-406, doi: 10.1109/ASP-DAC47756.2020.9045150 |