應用於單光子雪崩二極體之氮化鉭薄膜電阻器的特性探討

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陳盈如(Ying-Ru Chen) 查詢紙本館藏

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電機工程學系

論文名稱

應用於單光子雪崩二極體之氮化鉭薄膜電阻器的特性探討
(Deposition of tantalum nitride thin films as the integrated resistor for single photon avalanche diodes)

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摘要(中)

常見的薄膜電阻器材料有氮化鉭 (Tantalum nitride, TaN) 及鎳鉻(Nicochrome, NiCr) 薄膜，其廣泛應用於monolithic microwave integrated circuits (MMICs)及radio-frequency integrated circuit (RFICs)等電路中；早期在CMOS製程中，TaN被用來當作抵擋銅擴散的阻擋層，因TaN長期可靠度、良好熱與化學穩定性等因素，又能與CMOS製程相容，因此近來被用來做為高精度電阻器。
本論文目的在研究TaN薄膜電阻器的材料特性，其能應用於單光子雪崩二極體元件以減少寄生電容效應。單光子雪崩二極體是將雪崩二極體元件操作在崩潰電壓以上，以光激發載子透過碰撞電離 (Impact ionization) 過程，終發生雪崩崩潰引發大電流，屬於正回饋機制，此種機制使得崩潰電荷流非常大，導致嚴重的後脈衝 (afterpulse) 問題，從而限制了計數率；飽和的電荷流也使得單光子雪崩二極體喪失了光子數目解析之能力。
以薄膜電阻與單光子雪崩二極體做單晶片整合可實現負回饋雪崩機制，使雪崩過程受到調節，並逐漸回復待測狀態。方法是在單光子雪崩二極體結構最上層覆蓋一層薄膜電阻器，藉由引入類似被動截止電路之負載電阻，達到截止電路的效果，此法與被動截止電路不同的是，一般被動截止是通過混合集成電路 (hybrid integration) ，將伴隨較大的寄生效應，導致較大的電荷流。由於一個理想的單晶片集成所產生的電荷流 (Charge flow, Q) 和空乏電容 (Depletion capacitance, Cd) 還有過量偏壓 (Exccess bias, Vex) 成正比關係，故須降低寄生電容以降低電荷量，減少SPAD後脈衝效應之影響。
我們以不同氣體流量比、腔體壓力、濺鍍瓦數去沉積多組薄膜，並藉由量測薄膜電阻率、電阻率溫度係數、XRD分析與表面形態分析方式來探討不同參數下的薄膜品質，以獲得最適合應用於單光子崩潰二極體之薄膜沉積條件。

摘要(英)

The often used thin film resistor material includes tantalum nitride and nickel-chromium, which have been applied to monolithic microwave integrated circuits (MMICs) and radio-frequency integrated circuit (RFICs). In the early CMOS process, TaN was used as a barrier layer against copper diffusion. Due to the advantages of long-term reliability, good thermal and chemical stability, and compatibility with CMOS processes, TaN has been widely used as high precision resistors.
This thesis focuses on the study of the material properties of TaN thin-film resistors which can be monolithically integrated with single-photon avalanche diode (SPAD) to reduce parasitic capacitance effects. SPADs are operated above the breakdown voltage and can detect very faint light. The photon-generated carriers undergo a subsequent impact ionization process, eventually resulting a large current, which is a positive feedback mechanism. This mechanism generates substantial amount of charge flow, which can cause serious afterpulse problem, thereby limiting the counting rate. The saturated charge flow also makes the single-photon avalanche diode lose the ability of resolving the numbers of photon.
The monolithic integration of thin film resistors and SPAD can realize a negative feedback avalanche mechanism, which can regulate the avalanche process and gradually rearm the SPAD. The method is to deposit a thin film onto the top of the SPAD structure to introduce a load resistor similar to the passive quenching circuit, therefore the SPAD can be self-quenched during each avalanche. The difference between this method and the conventional passive quenching circuit (PQC) is that the PQC adopts hybrid integration which will have more serious parasitic effects, resulting in greater charge flow. Since the charge flow generated by an ideal single-chip integration is proportional to the overall capacitance and excess bias, the main task is to reduce the parasitic capacitance so as to reduce the amount of charge, and hence circumvent the afterpulsing effect.
The multiple sets of films with different gas flow ratios, chamber pressures, and sputtering power are deposited. Then we examined the film quality of different deposition parameters by film resistivity measurement, temperature coefficient of resistivity measurement, XRD analysis and surface morphology analysis to obtain the most suitable film deposition conditions for performing a high quality thin film resistor for SPADs.

關鍵字(中)

★ 單光子雪崩二極體
★ 負反饋雪崩二極體
★ 薄膜電阻器

關鍵字(英)

★ SPAD
★ NFAD
★ Thin Film Resistor

論文目次

目錄
中文摘要………………………………………………………………….i
英文摘要 Abstract……………………………………………………...iii
誌謝………………………………………………………………………v
目錄……………………………………………………………………..vii
圖目錄……………………………………………………………………x
表目錄……………………………………………………….………….xv
一、前言…………………………………………………………………1
1.1 研究背景…………………………………………………...1
1.2 論文架構…………………………………………………...2
二、負反饋雪崩二極體……………………………………………3
2.1 SPAD基本元件物理……………………………………….3
2.1.1 操作模式與I-V特性分析…………………………..3
2.1.2 蓋格模式下的崩潰機制……………………………..6
2.1.3 偵測器結構設計及電場分布………………………..9
2.2 元件操作截止電路………………………………………...10
2.2.1主動截止電路與被動截止電路…………………….10
2.2.2閘控模式電路…….………………………………….12
2.3 單片積體電路……………………………………………...14
2.3.1製造集成電阻的方法……………………………….15
2.4 負反饋雪崩二極體………………………………………...15
2.4.1瞬態載子緩衝區…………………………………….15
2.4.2薄膜電阻器集成之NFAD操作模式……………….16
2.4.3元件結構設計……………………………………….17
三、影響電阻率的原因…………………………………………..21
3.1 平均自由徑……………………………………………...21
3.2 電阻率溫度係數…………………………………………...22
3.3 馬西森定則………………………………………………...23
3.3.1 Electro-surface and sidewalls scattering…………….25
3.3.2 Grain boundary scattering………………………...26
3.3.3 Impurities scattering………………………………...28
四、實驗儀器原理…………………………………………………..29
4.1濺鍍基本原理…………..………………………………...29
4.2 XRD操作原理…………………………..………………...30
4.3 SEM操作原理……………………………………..…….32
4.4 四點探針電阻值量測系統…………………………..…….33
4.5 原子力顯微鏡基本原理………………………………….35
五、文獻回顧………………………..………………………………..37
六、實驗流程與量測結果…………………………………………..46
6.1實驗流程…………….………………………………………46
6.2元件製程參數……….………………………………………48
6.2.1沉積參數………………………………………….48
6.2.2薄膜沉積速率...…………………………………….50
6.3 薄膜電阻值….…………………………………………54
6.3.1常溫之薄膜電阻值………………………………….54
6.3.2變溫之薄膜電阻值………………………………….56
6.3.3電阻率溫度係數...………………………………….60
6.4 SEM 分析…….…………………....………………...……65
6.5 AFM 分析……………..…………..………………...……71
6.6 XRD分析…………………………………………………73
6.7 晶粒尺寸…………………………………………………76
七、結論與未來展望………………………………………………..78
參考文獻………………………………………………………………..79

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指導教授

李依珊(Yi-Shan Lee)

審核日期

2021-8-25

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