博碩士論文 108521027 詳細資訊




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姓名 李艾芳(Ai-Fang Li)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於非揮發性鐵電靜態隨機存取記憶體之變異容忍性召回操作
(Variation-Tolerant Recall Operation for Nonvolatile Ferroelectric-based SRAM)
相關論文
★ 鐵電場效電晶體記憶體考慮金屬功函數變異度之分析★ 分析與設計低電壓操作之非揮發性鐵電場效電晶體記憶體
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摘要(中) 2013年德國政府提出「工業 4.0」的高科技計畫,可大幅改善傳統生產製造效率,為了能有效處理大量的資料,高效率及快速讀寫的設備扮演著重要的角色。其中SRAM具有快速讀寫的優勢,若能在斷電後仍能保留資料,便可大幅的降低功率耗損。近年來鐵電材料因與目前CMOS技術具有兼容性且可微縮的優勢,其中鐵電非揮發性SRAM極具潛力同時達到快速操作及超低功耗等功能需求。

本篇論文著重探討兩種6T2C NVSRAM的召回操作設計(Type-1及Type-2),並利用TCAD模擬軟體結合Preisach model來模擬鐵電電容。考慮在最嚴苛的閾值電壓變異(△VTH)情況下,比較電晶體變異對兩種NVSRAM召回操作的影響。結果顯示當增加剩餘極化(Pr)、減少鐵電介電係數(εFE)或矯頑電場(Ec),召回操作表現上可獲得更好的變異度免疫力。除此之外,Type-2召回操作在優化的鐵電電容面積下,當飽和極化(Ps)接近剩餘極化時,可容忍閾值電壓變異度為116 mV,比Type-1召回操作大4.46倍。

在附錄部分,我們提出記憶體視窗(Memory window)模型架構,透過數學模型去分析不同鐵電材料參數在飽和迴圈下,對非揮發性鐵電場效電晶體記憶視窗的影響,結果顯示在足夠電壓情況下,當剩餘極化或矯頑電場增加時,可增加記憶視窗及鐵電記憶的穩定性。
摘要(英) Industry 4.0 was proposed by the German government in 2013, which can improve the efficiency of conventional industries. To process lots of data, low power consumption and high-speed devices play essential roles. The SRAM possesses the advantage of high speed. If it can recover the data after the power down, the power consumption will be reduced. Recently, ferroelectric-based materials have been widely studied for nonvolatile memory applications because of their advantage of high CMOS compatibility. Therefore, ferroelectric nonvolatile SRAM (FE-NVSRAM) presents great potential to meet the requirements of high-speed operation and low-power consumptions.

This work compares different recall operations for 6T2C NVSRAM using the TCAD simulation with the Preisach model. For the first time, we have studied the impact of device variations on the recall operations. Two recall schemes (Type-1 and Type-2) are compared, considering the worst threshold mismatch (∆VTH) scenarios. During the recall operation, as the Ec and εFE reduce, or Pr increases, the NVSRAM shows higher immunity to threshold mismatch. Besides, the Type-2 recall scheme with the optimized ferroelectric area can tolerate 116mV threshold voltage mismatch, which is 4.46 times larger than the Type-1 recall scheme.

In the appendix, we have proposed a framework to analyze the impact of various device parameters on the memory window of FeFET in the saturation loop. The memory window (MW) can increase with the rising of Ec and Pr when sufficient voltage supply is used to program the FeFET, which enhances the MW and improves the reliability.
關鍵字(中) ★ 非揮發性靜態隨機存取記憶體
★ 鐵電電容
★ 變異容忍性
★ 記憶視窗
關鍵字(英) ★ nonvolatile SRAM (NV-SRAM)
★ ferroelectric capacitor
★ variation-tolerant
★ memory window (MW)
論文目次 摘要 I
Abstract II
致謝 III
圖目錄 VII
第一章導論 1
1.1 背景與相關研究 1
1.1.1 鐵電材料 2
1.1.2 非揮發性靜態隨機存取記憶體介紹 4
1.1.3 鐵電非揮發性靜態隨機存取記憶體應用及操作 5
1.1.4 鐵電記憶體資料保存時間 9
1.2 研究動機 14
1.3 論文架構 15
第二章 鐵電模型介紹 16
2.1 前言 16
2.2 鐵電模型分類 16
2.2.1 L-K Model 模擬架構介紹 18
2.2.2 Preisach Model 模擬架構介紹 20
2.3 結論 27
第三章 鐵電非揮發性靜態隨機存取記憶體單元操作分析 28
3.1 前言 28
3.2 鐵電非揮發性靜態隨機存取記憶體操作 29
3.3 元件結構與模擬參數 34
3.4 儲存操作對鐵電電容影響 36
3.5 鐵電參數對召回操作影響 40
3.5.1 鐵電電容面積與鐵電參數對Type-2召回操作影響 41
3.5.2 鐵電電容參數與面積對閾值電壓變化容忍度影響 44
3.6 結論 65
第四章 總結 66
參考文獻 68
附錄 非揮發性鐵電場效電晶體記憶體於飽和迴圈之記憶視窗分析 74
參考文獻 [1] I.R. Committee, "International Roadmap for Devices and Systems," 2020 Edition. More Moore white paper.
[2] T. Hiramoto, K. Takeuchi, T. Mizutani et al., "Ultra-low power and ultra-low voltage devices and circuits for IoT applications," 2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, pp. 146-147.
[3] S. S. Eaton, D. B. Butler, M. Parris et al., "A ferroelectric nonvolatile memory," 1988 IEEE International Solid-State Circuits Conference (ISSCC), 1988, pp. 130–131.
[4] C. Liu, Q. Wang, J. Yang et al., "A 7T1C Nonvolatile SRAM Based on Ferroelectric HfO2 Capacitor for Ultralow Power Applications," 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020, pp. 1-3.
[5] T. Miwa, J. Yamada, H. Koike et al., "A 512 kbit low-voltage NV-SRAM with the size of a conventional SRAM," 2001 IEEE Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001, pp. 129–132.
[6] S. Masui, W. Yokozeki, M. Oura et al., "Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall," 2003 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2003, pp. 403–406.
[7] T. S. Böscke, J. Müller, D. Bräuhaus et al.,“Ferroelectricity in hafnium oxide thin films,” 2001 Applied Physics Letters (AIP), vol. 99, no. 10, p. 102903, Sep. 2011.
[8] A. Toriumi, L. Xu, Y. Mori et al., "Material perspectives of HfO2-based ferroelectric films for device applications," 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp. 15.1.1-15.1.4.69
[9] S. Mueller, J. Müller, U. Schroeder et al., "Reliability Characteristics of Ferroelectric Si:HfO2 Thin Films for Memory Applications," 2013 IEEE Transactions on Device and Materials Reliability, vol. 13, no. 1, pp. 93-97, March 2013.
[10] S. L. Miller, R. D. Nasby, J. R. Schwank et al., "Device modeling of ferroelectric capacitors," 1990 Journal of Applied Physics (AIP), vol. 68, no. 12, 1990, pp. 6463–6471.
[11] R. Alguliyev, Y. Imamverdiyev, and L. Sukhostat, "Cyber-physical systems and their security issues," 2018 Computers in Industry, vol. 100, pp. 212-223, September 2018.
[12] P. F. Chiu, M. F. Chang, C. W. Wu et al., "Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications," 2012 IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 6, pp. 1483–1496, Jun. 2012.
[13] Y. Shuto, S. Yamamoto, and S. Sugahara, "Nonvolatile static random access memory based on spin-transistor architecture," 2009 Journal of Applied Physics (AIP), vol. 105, no. 7, pp. 07C933, April 2009.
[14] G. W. Burr, M. J. Brightsky, A. Sebastian et al., "Recent progress in phase-change memory technology," 2016 IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 2, pp. 146–162, Jun. 2016.
[15] S. Masui, T. Ninomiya, M. Oura et al., "A ferroelectric memory-based secure dynamically programmable gate array," 2003 IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 5, pp. 715-725, May. 2003.
[16] W. You, P. Su and C. Hu, "A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET," 2020 IEEE Journal of the Electron Devices Society (JEDS), vol. 8, 2020, pp. 171-175.
[17] C. Liu, J. Yang, P. Jiang et al., "A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme," 2020 IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 28, no. 11, pp. 2469-2473, Nov. 2020.
[18] T. Miwa, J. Yamada, H. Koike et al., "NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors," 2001 IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 522-527, Mar. 2001.
[19] M. Kobayashi, N. Ueyama and T. Hiramoto, "A nonvolatile SRAM integrated with ferroelectric HfO2 capacitor for normally-off and ultralow power IoT application," 2017 IEEE Symposium on VLSI Technology, 2017, pp. T156-T157.
[20] K. Florent, S. Lavizzari, L. D. Piazza et al., "Reliability Study of Ferroelectric Al:HfO2 Thin Films for DRAM and NAND Applications", 2017 IEEE Transactions on Electron Devices, vol. 64, no. 10, 2017, pp.
4091-4098.
[21] H. Mulaosmanovic, P. D. Lomenzo, U. Schroeder et al., "Reliability aspects of ferroelectric hafnium oxide for application in nonvolatile memories", 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6.
[22] J. Müller, P. Polakowski, J. Paul et al., "Integration challenges of ferroelectric hafnium oxide based embedded memory," 2015 Electrochemical Society Transactions (ECST), vol. 69, no. 3, pp. 85–95, Oct. 2015.
[23] X. Pan and T. P. Ma, "Retention mechanism study of the ferroelectric field effect transistor," 2011 Applied Physics Letters (AIP), vol. 99, no. 1, 2011, p. 01305.
[24] P. D. Lomenzo, S. Slesazeck, M. Hoffmann et al., "Ferroelectric Hf1-xZrxO2 memories: device reliability and depolarization fields," 2019 IEEE 19th Nonvolatile Memory Technology Symposium (NVMTS), 2019, pp. 1-8.
[25] N. Gong and T. Ma, "Why Is FE–HfO2 More Suitable Than PZT or SBT for Scaled Nonvolatile 1-T Memory Cell? A Retention Perspective," 2016 IEEE Electron Device Letters, vol. 37, no. 9, 2016, pp. 1123-1126.
[26] Sentaurus Device User Guide, O-2018.06, Synopsys, Jun. 2018.
[27] A. Mallick and N. Shukla, "Evaluation of Bulk and SOI FeFET Architecture for Nonvolatile Memory Applications," 2019 IEEE Journal of the Electron Devices Society (JEDS), vol. 7, 2019, pp. 425-429.
[28] S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices," 2008 Nano Letters, vol. 8, no. 2, pp. 405–410, Dec. 2008.
[29] K. Ni, M. Jerry, J. A. Smith et al., "A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs," 2018 IEEE Symposium on VLSI Technology, 2018, pp. 131-132.
[30] H. Mulaosmanovic, J. Ocker, S. Müller et al., "Switching kinetics in nanoscale hafnium oxide based ferroelectric field-effect transistors," 2017 Applied Materials & Interfaces (ACS), vol. 9, no. 4, 2017, pp. 3792-3798.
[31] M. -H. Yan, M. -H Wu, H. -H Huang et al., "BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 4.6.1-4.6.4.
[32] J. Chow, A. Sheikholeslami, J. S. Cross et al., "A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits," 2004 IEEE Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), pp. 448-449, July. 2004.
[33] H. Mulaosmanovic, S. Dünkel, M. Trentzsch et al., "Investigation of Accumulative Switching in Ferroelectric FETs: Enabling Universal Modeling of the Switching Behavior," 2020 IEEE Transactions on Electron Devices (TED), vol. 67, no. 12, pp. 5804-5809, Dec. 2020.
[34] N. Gong, X. Sun, H. Jiang et al., "Nucleation limited switching (NLS) model for HfO2-based metal ferroelectric-metal (MFM) capacitors: Switching kinetics and retention characteristics," 2018 Applied Physics Letters (AIP), vol. 112, no. 26, 2018, p. 262903.
[35] J. Wu, H. Zhong, K. Ni, et al., "A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs," 2019 IEEE Design Automation Conference (DAC), 2019, pp. 1-6.
[36] C. Kuhn, H. Honigschmid, O. Kowarik et al., "A dynamic ferroelectric capacitance model for circuit simulators," 2000 IEEE International Symposium on Applications of Ferroelectrics (IEEE Cat. No.00CH37076), vol. 2, 2000, pp. 695-698.
[37] M. Jerry, PY. Chen, J. Zhang et al., "Ferroelectric FET analog synapse for acceleration of deep neural network training," 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 6.2.1-6.2.4.
[38] M. Kobayashi, N. Ueyama, K. Jang et al., "Experimental Demonstration of a Nonvolatile SRAM With Ferroelectric HfO2 Capacitor for Normally Off Application," 2018 IEEE Journal of the Electron Devices Society (JEDS), vol. 6, pp. 280-285, 2018.
[39] S. S. Eaton, D. B. Butler, M. Parris et al., "A ferroelectric nonvolatile memory," 1988 IEEE International Conference on Solid-State Circuits (ISSCC) Dig. Tech. Papers, Feb. 1988, pp. 130–131.
[40] H. Jiang, O. Li, W. Chen et al., "Dual-Storage-Port Nonvolatile SRAM Based on Back-End-of-the-Line Processed Hf0.5Zr0.5O₂ Ferroelectric Capacitors Towards 3D Selector-Free Cross-Point Memory," 2020 IEEE Journal of the Electron Devices Society (JEDS), vol. 8, pp. 935-938, 2020.
[41] T. Ali, P. Polakowski, K. Kühnel et al., "A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 28.7.1-28.7.4.
[42] C. Jin, T. Saraya, T. Hiramoto et al., "On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region," 2019 IEEE Journal of the Electron Devices Society (JEDS), vol. 7, pp. 368-374, 2019.
[43] B. Jiang, Zurcher, Jones et al., "Computationally Efficient Ferroelectric Capacitor Model For Circuit Simulation," 1997 Symposium on VLSI Technology, 1997, pp. 141-142.
[44] S. Masui, T. Ninomiya, M. Oura et al., "Ferroelectric memory based secure dynamically programmable gate array," 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002, pp. 200-203.
[45] K. Takeuchi, M. Kobayashi and T. Hiramoto, "A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability-Aware Design Optimization," 2019 IEEE Journal of the Electron Devices Society (JEDS), vol. 7, pp. 1284-1292, 2019.
指導教授 胡璧合 李依珊(Vita Pi-Ho Hu Yi-Shan Lee) 審核日期 2021-11-29
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