具資料決策補償技術之16 Gbps半速率時脈與資料回復電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：23

、訪客IP：3.147.75.40

姓名

王璽華(Hsi-Hua Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具資料決策補償技術之16 Gbps半速率時脈與資料回復電路
(A 16 Gbps Half-Rate Clock and Data Recovery with Data Decision Compensation Technique)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

製程隨著莫爾定律發展，晶片中可容納更多電晶體，運算能力大幅提升，因此資料處理及傳輸量倍增。高速串列傳輸已成為傳輸介面的主流並逐漸替代傳統的並列傳輸。例如：PCI-Express、USB、SATA、HDMI、DisplayPort及Ethernet等。傳輸速率不斷倍增下，符碼間干擾產生的影響越來越嚴重以及電路的時間容忍區間也越來越小，惡化誤碼率及抖動容忍度，因此如何維持抖動容忍度及降低誤碼率的發生是必須克服的議題。
本論文根據PCIe 4.0規格實現一個具資料決策補償技術之16 Gbps半速率時脈與資料回復電路。決策電路將多階二進位相位偵測器產生的輸出進行運算，得到輸入資料與還原時脈的相位差，透過選擇不同相位的時脈對資料取樣，避免取樣到資料轉態緣，提升抖動容忍度並降低誤碼率；藉由決策電路判斷相位差是否大於0.5 UI，決定交換式二進位相位偵測器的領先落後資訊是否要進行交換，使迴路在相位差大於0.5 UI時仍可往正確方向追鎖。透過此技術不僅可以使相位偵測器可容忍的相位差範圍從0.5 UI 增加至1.0 UI，亦可超過傳統時脈與資料回復電路於高頻抖動容忍度僅能達到0.5 UI的限制。本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程，操作電壓為0.9 V，輸入資料為PRBS7 16 Gbps，佈局後模擬高頻抖動容忍度與傳統時脈與資料回復電路相比可以改善100 %。量測還原時脈速率為8 GHz，還原時脈之抖動峰對峰值為9.11 pspp，方均根值為1.28 psrms，功率消耗為47.88 mW，晶片面積為0.998 mm2，核心電路面積為0.078 mm2。

摘要(英)

With the development of Moore′s Law, the semiconductor technology allows more transistors in the chip. The computing power of the chip has been greatly improved, so the processing and transmission of data has increased. High-speed serial link becomes the mainstream of the transmission interface and gradually replaces the traditional parallel communication. For example: PCI-Express, USB, SATA, HDMI, DisplayPort and Ethernet, etc. As the data rate increases, the influence of inter-symbol interference (ISI) becomes serious, and the time tolerance interval of the circuit becomes small. Consequently, bit error rate (BER) and jitter tolerance (JTOL) are degraded. How to maintain jitter tolerance and reduce the bit error rate is an issue that must be overcome.
This thesis presents a 16 Gbps half-rate clock and data recovery with data decision compensation technique which takes the PCIe 4.0 specification as a reference material. The proposed decision controller operates the output signal generated by the multi-level bang-bang phase detector (ML BBPD) to obtain the phase error between the data and the recovered clock. Selecting clocks of different phases to sample the data can avoid sampling near the transition edge of the data which improves jitter tolerance and reduces bit error rates. According to whether the phase error is greater than 0.5 UI, the decision controller decides whether the UP and DN signal of the swapping bang-bang phase detector (SBBPD) should be exchanged. Therefore, when the phase error is greater than 0.5 UI, the loop can still be tracked in the correct direction. This technique not only increase the phase error tolerance of the phase detector from 0.5 UI to 1.0 UI, but also exceed the high-frequency jitter tolerance limit of the traditional CDR which is only 0.5 UI. In this thesis, we used TSMC 40 nm (TN40G) 1P10M CMOS process with 0.9 V supply voltage to fabricate the chip and the input data is PRBS7 16 Gbps NRZ signal. In the post-layout simulation, high-frequency jitter tolerance compared to conventional bang-bang CDR is improved by 100 %. At 8 GHz, the measured jitter of the recovered clock is 9.11 pspp and 1.28 psrms, and the power consumption is 47.88 mW. The chip area is 0.998 mm2 and the core area is 0.078 mm2.

關鍵字(中)

★ 時脈與資料回復電路
★ 抖動容忍度優化
★ 二進位相位偵測器

關鍵字(英)

★ Clock and Data Recovery
★ Jitter Tolerance Enhance
★ Bang-Bang Phase Detector

論文目次

摘要----------------------------------------------------i
Abstract-----------------------------------------------ii
誌謝---------------------------------------------------iv
目錄---------------------------------------------------vi
圖目錄-------------------------------------------------ix
表目錄-----------------------------------------------xiii
第1章緒論----------------------------------------------1
1.1 研究動機--------------------------------------------1
1.2 論文架構--------------------------------------------4
第2章高速串列傳輸訊號介紹--------------------------------5
2.1 隨機二位元資料介紹-----------------------------------5
2.1.1 隨機二位元資料型態---------------------------------5
2.1.2 隨機二位元資料特性---------------------------------6
2.1.3 資料編碼機制---------------------------------------7
2.2 抖動介紹--------------------------------------------8
2.2.1 隨機性抖動----------------------------------------9
2.2.2 定量性抖動---------------------------------------10
2.2.3 抖動量測方式--------------------------------------13
2.3 眼圖分析-------------------------------------------18
2.4 誤碼率[17]-----------------------------------------19
第3章時脈與資料回復電路背景介紹-------------------------22
3.1 時脈與資料回復電路簡介------------------------------22
3.1.1 相位偵測器操作型態--------------------------------23
3.1.2 相位偵測器取樣速率--------------------------------24
3.1.3 抖動轉移函數(Jitter Transfer, JTF)----------------25
3.1.4 抖動容忍度(Jitter Tolerance, JTOL)----------------26
3.1.5 抖動產生(Jitter Generation)-----------------------28
3.2 傳統時脈與資料回復電路相關設計------------------------28
3.2.1 鎖相迴路式時脈與資料回復電路-----------------------28
3.2.2 混合鎖相迴路及延遲鎖定迴路式時脈與資料回復電路-------30
3.2.3 超取樣式時脈與資料回復電路-------------------------31
3.2.4 相位內插器式時脈與資料回復電路----------------------32
3.2.5 突發模式時脈與資料回復電路-------------------------33
3.2.6 頻率資訊迴路--------------------------------------33
3.3 提升抖動容忍度之相關設計-----------------------------35
3.3.1 多增益路徑之超取樣式時脈與資料回復電路---------------35
3.3.2 自適應迴路增益之時脈與資料回復電路------------------36
3.4 比較與討論------------------------------------------37
第4章具資料決策補償技術之半速率時脈與資料回復電路設計與實現-40
4.1 電路架構--------------------------------------------40
4.2 系統分析--------------------------------------------42
4.2.1 頻率資訊迴路系統分析-------------------------------42
4.2.2 相位資訊迴路系統分析-------------------------------46
4.3 資料決策補償技術操作說明-----------------------------52
4.3.1 傳統二進位相位偵測器分析之時脈與資料回復電路---------52
4.3.2 資料決策補償技術分析-------------------------------53
4.4 行為模擬--------------------------------------------55
4.5 子電路介紹------------------------------------------58
4.5.1 資料決策補償回復電路-------------------------------58
4.5.2 半速率多階交換式二進位相位偵測器--------------------64
4.5.3 電荷幫浦------------------------------------------67
4.5.4 電容放大技術之迴路濾波器----------------------------69
4.5.5 壓控振盪器----------------------------------------70
4.5.6 相位頻率偵測器-------------------------------------72
4.5.7 除頻器--------------------------------------------74
4.5.8 擺幅轉換電路---------------------------------------75
4.6 模擬結果---------------------------------------------75
4.6.1 佈局前模擬結果-------------------------------------76
4.6.2 佈局後模擬結果-------------------------------------79
第5章晶片佈局及量測--------------------------------------82
5.1 電路佈局---------------------------------------------82
5.1.1 晶片封裝-------------------------------------------83
5.1.2 佈局及電源規劃-------------------------------------84
5.2 量測考量---------------------------------------------86
5.2.1 量測環境-------------------------------------------86
5.2.2 印刷電路板-----------------------------------------87
5.2.3 高頻輸入端-----------------------------------------88
5.2.4 高頻輸出緩衝器-------------------------------------89
5.2.5 低頻輸出緩衝器-------------------------------------90
5.3 晶片與印刷電路板照相圖--------------------------------91
5.4 量測結果---------------------------------------------92
5.4.1 鎖相迴路量測結果-----------------------------------92
5.4.2 時脈與資料回復電路量測結果--------------------------94
5.4.3 量測結果討論與分析----------------------------------95
5.5 規格比較表-------------------------------------------98
第6章結論-----------------------------------------------100
6.1 結論------------------------------------------------100
6.2 未來研究方向-----------------------------------------101

參考文獻

[1]DisplayPort (DP) Standard, Version 2.0, VESA, 2019
[2]High-Definition Multimedia Interface Specification, Version 2.0, HDMI, 2013
[3]PCI Express® Base Specification, Revision 4.0 Version 0.7, PCI-SIG, 2016.
[4]Serial ATA International Organization, Serial ATA Revision 3.2, SATA-IO, 2013.
[5]Universal Serial Bus 4 Specification, Version, USB-IF, 2019.
[6]孫世洋, “以符碼間干擾技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[7]B. Razavi, Design of Integrated Circuits for Optical Communications, 1st ed. New York, NY, USA: McGraw-Hill, 2003.
[8]A. X. Widmer, and P. A. Franaszek, “A DC-balanced, partitioned-block, 8b/10b transmission code,” IBM J. Res and Develop., vol. 27, pp. 440-451, Sept. 1983.
[9]Tektronix, “Understanding and characterizing timing jitter”.
[10]N. Da Dalt and A. Sheikholeslami, Understanding Jitter and Phase Noise a Circuits and Systems Perspective, Cambridge, U.K. Cambridge Univ. Press, 2018.
[11]Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[12]B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017.
[13]R. Sarpeshkar, T. Delbruck and C. A. Mead, “White noise in MOS transistors and resistors,” IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, Nov. 1993.
[14]Maxim, “Choosing AC-Coupling Capacitors,” Application Note: HFAN-1.1, 2000.
[15]N. Radhakrishnan, B. Achkir, J. Fan and J. L. Drewniak, “Stressed jitter analysis for physical link characterization,” in Proc. IEEE International Symposium on Electromagnetic Compatibility, Feb. 2010, pp. 568-572.
[16]STMicroelectronics, “Improving a jitter definition,” 2007.
[17]SHF Communication Technologies AG, “Application note AN-jitter-1-jitter analysis using SHF 10000 series bit error rate testers,” 2005.
[18]Agilent Technologies, “Measuring jitter in digital systems,” Application Note 1448-1.
[19]劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.
[20]K. S. Kwak, and O. K. Kwon, “Power-reduction technique using a single edge-tracking clock for multiphase clock and data recovery circuit,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 4, pp. 239–243, Apr. 2014.
[21]鄭宇亨, “具資料獨立相位追蹤補償技術之 10 Gbps 半速率時脈與資料回復電路,”碩士論文, 國立中央大學, 2018.
[22]R. C. Walker and B. Razavi, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems,” in Proc. High-Performance Systems, Feb. 2003, pp.34-45.
[23]J. Lee, K. S. Kundert and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sept. 2004.
[24]T. Lee, Y. -H. Kim and L. -S. Kim, “A 5-Gb/s digital clock and data recovery circuit with reduced DCO supply noise sensitivity utilizing coupling network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 380-384, Jan. 2017.
[25]X. Ge, Y. Chen, X. Zhao, P. -I. Mak and R. P. Martins, “Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2223-2236, Oct. 2019.
[26]T. H. Lee and J. F. Bulzacchelli, “A 155 MHz clock recovery delay- and phase-locked loop,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Dec. 1992, pp. 160-161.
[27]J. Lin, C. Yang and H. Wu, “A 2.5-Gb/s DLL-based burst-mode clock and data recovery circuit with 4 × oversampling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, pp. 791-795, April 2015.
[28]W. Bae, G. Jeong, K. Park, S. Cho, Y. Kim and D. Jeong, “A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s forwarded-clock receiver with a stuck-free delay-locked loop and a half-bit delay line in 65-nm CMOS technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 9, pp. 1393-1403, Sept. 2016.
[29]Y. -S. Lin, M. -S. Li and C. -Y. Yang, “A 2.7-Gb/s clock and data recovery circuit based on D/PLL,” in IEEE International System-on-Chip Conference, Sept. 2019, pp. 284-288.
[30]J. Kim, and D.-K. Jeong, “Multi-gigabit-rate clock and data recovery based on blind oversampling,” IEEE Commun. Mag., vol. 41, pp. 68–74, Dec. 2003.
[31]G. Wu et al., “A 1–16 Gb/s all-digital clock and data recovery with a wideband high-linearity phase interpolator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2511-2520, July 2016.
[32]J. Terada, K. Nishimura, S. Kimura, H. Katsurai, N. Yoshimoto and Y. Ohtomo, “A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2921-2928, Dec. 2008.
[33]K. Kishine et al., “A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 5, pp. 1288-1295, May 2015.
[34]Y. S. Tan, K. S. Yeo, C. C. Boon and M. A. Do, “A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 6, pp. 1156-1167, June 2012.
[35]R. Inti, W. Yin, A. Elshazly, N. Sasidhar and P. K. Hanumolu, “A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance,” IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 3150-3162, Dec. 2011.
[36]M. Brownlee, P. K. Hanumolu and U. Moon, “A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance,” in IEEE Custom Integrated Circuits Conference, Sept. 2007, pp. 353-356.
[37]D. Kwon, Y. Park and W. Choi, “A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 6, pp. 1472-1480, June 2015.
[38]C. Gimeno, D. Bol and D. Flandre, “Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 9, pp. 1807-1811, Sept. 2018.
[39]H. -J. Jeon, R. Kulkarni, Y. -C. Lo, J. Kim and J. Silva-Martinez, “A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy,” IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1398-1415, June 2013.
[40]Y. -S. Yao, C. -C. Huang and S. -I. Liu, “A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1837-1841, June 2021.
[41]鄭柏旻, “具電容放大技術和自適應迴路增益控制器之5 Gbps雙路徑時脈與資料回復電路,” 碩士論文, 國立中央大學, 2017.
[42]Integrated Device Technology Inc, “RMS Phase Jitter,’’ Aplication Note, AN-839, 2014.
[43]J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE Journal of Solid-State Circuits, Express Briefs, vol. 39, no. 9, pp. 1571–1580, Sept. 2004.
[44]謝文軒, “具資料及邊緣符碼間干擾補償之28 Gbps四階脈波振幅調變自適應等化器,”碩士論文, 國立中央大學, 2020.
[45]Y. Kim et al., “An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 823-835, April 2017.
[46]Z. Shu et al., “A 5–13.5 Gb/s Multistandard Receiver with High Jitter Tolerance Digital CDR in 40-nm CMOS Process,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 10, pp. 3378-3388, Oct. 2020.
[47]H. -R. Kim et al., “A 6.4–11 Gb/s Wide-Range Referenceless Single-Loop CDR with Adaptive JTOL,” IEEE Solid-State Circuits Letters, vol. 3, pp. 470-473, 2020.
[48]W. -M. Chen et al., “A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR with One-Tap DFE,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 894-898, Mar. 2022.
[49]W. -M. Chen et al., “A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 11, pp. 4566-4575, Nov. 2021.
[50]A. M. Fahim, “A compact, low-power low-jitter digital PLL,” in Proc. IEEE European Solid-State Circuit Conference, Sept. 2003, pp. 101–104.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2022-8-11

推文