博碩士論文 108521052 詳細資訊




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姓名 柯瀚(Han Ke)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 基於蛙跳演算法及穩定性準則之高成本效益迴音消除器設計
(A High Cost-Efficient Design of Echo Canceller Based on Shuffled Frog Leaping Algorithm and Stability Criterion)
相關論文
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摘要(中) 高速以太網傳輸系統中,如5GBASE-T系統,迴音干擾和近端干擾(NEXT)是兩個主要議題。本論文依據 IEEE 802.3bz™-2016 規範標準 [1],設計出乙太網路傳輸之數位基頻收發機晶片來送收PAM-16編碼之訊號。傳統方法使用自適應有限脈衝(Finite Impulse Response, FIR)濾波器複製迴音路徑之通道效應,使通過迴音路徑與通過迴音消除器之訊號相同,進而扣除迴音。惟使用傳統方法將因有限脈衝濾波器長度過長而花費大量硬體成本,因此如何在符合規範效能下有效地降低硬體成本將是首要課題。本論文所採用之迴音通道模型,在尾段(Tail)部分有因近端(Near end)與遠端(Far end)傳輸不匹配造成之小幅度反射波(Reflection),且反射波位置將因通道長度不同而有所改變,因此現存文獻提出之方法無法達到期望之效能,抑或是電路成本居高不下。本論文使用有限脈衝響應(FIR)、無限脈衝響應(Infinite Impulse Response, IIR)濾波器進行模擬分析,藉由穩定性準則克服無限脈衝響應濾波器可能造成系統無法收斂之情形,而近年來人工智慧相關技術蓬勃發展,本論文亦結合機器學習與自適應濾波器,在既符合規範標準下,降低迴音消除器電路之成本。
硬體實現之部分使用Verilog HDL描述與模擬,透過SMIMS VeriEnterprise Xilinx FPGA與晶片設計工具Design Compiler與IC Compiler在TSMC-40nm製程下驗證其電路功能。
摘要(英) In many high speed Ethernet transmission systems, such as 5 GBASE-T system, echo and near-end crosstalk (NEXT) interferences are two major impairments. This work designs the digital baseband transceiver for Ethernet transmission using PAM-16 signal based on standard IEEE 802.3bz™-2016. Conventional echo cancellation is performed using noise cancellers which are usually implemented using adaptive finite impulse response (FIR) filters, where the replica of echo interferences estimated by FIR filters are subtracted from the received noisy signals. This traditional approach, however, requires a significant hardware cost as the number of taps in the adaptive FIR filters is large. Therefore, it is important to reduce hardware cost. The issue of how to decrease the cost of the circuit while meeting the performance requirements has been paid more and more attention. The echo channel model used in this paper has a small reflection in the tail part due to the mismatch between the transmission of the near end and the far end echo. Position of the reflection will be determined by the cable length, so the methods proposed in the traditional literature cannot achieve the desired performance, or the circuit cost remains high. In this paper, finite impulse response and infinite impulse response filters are used for simulation analysis, and the stability criterion is used to avoid the unstable situation. In recent years, artificial intelligence related technologies are developing vigorously. This paper also combines machine learning and adaptive filters to decrease the cost of echo canceller circuits.
Regarding the hardware implementation, the Verilog HDL description is employed and the related simulations, are conducted. The circuit function is verified under the TSMC-40nm process through SMIMS VeriEnterprise Xilinx FPGA and chip design tools Design Compiler and IC Compiler.
關鍵字(中) ★ 迴音消除器
★ 乙太網路
★ 有限脈衝響應濾波器
★ 無限脈衝響應濾波器
關鍵字(英) ★ Echo canceller
★ Echo cancellation
★ Ethernet
★ 802.3bz
★ FIR filter
★ IIR filter
論文目次 摘要 i
Abstract ii
致謝 iii
圖目錄 viii
表目錄 xiii
第一章 緒論 1
1.1背景 1
1.2 研究動機 1
1.3 論文貢獻 2
第二章 迴音消除器電路介紹 3
2.1迴音消除器電路系統概要 3
2.2有限脈衝響應電路架構 6
2.3無限脈衝響應電路架構 7
第三章 迴聲消除器演算法介紹 10
3.1 最小均方(LMS)演算法 10
3.2 延遲最小均方(Delayed-LMS) 12
3.3 蛙跳演算法(Shuffled frog leaping algorithm, SFLA) 13
第四章 考量類比效應之改良迴音通道架構 17
4.1 巴特沃斯濾波器(Butterworth Filter) 17
4.2 切比雪夫濾波器(Chebyshev Filter) 17
4.3 規範之傳輸端功率頻譜密度遮罩(Transmitter Power Spectral Density Mask) 18
4.4 接收端之頻外干擾(Receiver Out of Band Interference) 21
4.5 結合傳輸與接收端應用之改良迴音通道架構 22
第五章 Jury穩定性準則 25
5.1無限脈衝響應濾波器之不穩定性 25
5.2 Jury穩定性準則(Jury Stability Criterion) 31
5.3結合Jury穩定性準則之蛙跳演算法架構 33
第六章 提出之改良架構與模擬結果 38
6.1暫存元件數量之決定方法與架構 38
6.2可共用型濾波器電路架構 43
6.2.1 Main canceller內部架構 44
6.2.2 Tail canceller內部架構 45
6.3 蛙跳演算法與Jury穩定性準則架構 45
6.4模擬環境 47
6.4.1十公尺模擬環境 48
6.4.2二十公尺模擬環境 49
6.4.3三十公尺模擬環境 50
6.4.4四十公尺模擬環境 51
6.4.5五十公尺模擬環境 52
6.4.6六十公尺模擬環境 53
6.4.7七十公尺模擬環境 54
6.4.8八十公尺模擬環境 55
6.4.9九十公尺模擬環境 56
6.4.10一百公尺模擬環境 57
6.5模擬結果 58
6.5.1十公尺模擬結果 58
6.5.2二十公尺模擬結果 58
6.5.3三十公尺模擬結果 59
6.5.4四十公尺模擬結果 59
6.5.5五十公尺模擬結果 60
6.5.6六十公尺模擬結果 60
6.5.7七十公尺模擬結果 61
6.5.8八十公尺模擬結果 61
6.5.9九十公尺模擬結果 62
6.5.10一百公尺模擬結果 62
6.5.11十到一百公尺長度之模擬結果 63
6.6架構比較 69
第七章 電路架構與晶片實現 70
7.1電路設計流程 70
7.2硬體電路介紹 71
7.2.1共用更新演算法之有限脈衝響應濾波器架構 72
7.2.2無限脈衝響應濾波器與蛙跳演算法係數儲存架構 74
7.3暫存元件架構 75
7.4預先載入無限脈衝響應濾波器係數架構 76
7.5比較電路、更新電路與穩定性電路架構 77
7.6模擬驗證 78
7.7晶片設計結果 80
7.7.1佈局圖 80
7.7.2模組分布 81
7.7.3錯誤覆蓋率 83
7.7.4 LVS驗證結果 83
7.7.5 CHIP功率消耗分佈 84
7.7.6 CHIP 總結 86
第八章 結論與未來展望 87
參考文獻 88
參考文獻 [1] IEEE Standard for Ethernet Amendment 7: Media Access Control Parameters,
Physical Layers, and Management Parameters for 2.5 Gb/s and 5 Gb/s Operation,
Types 2.5GBASE-T and 5GBASE-T. [2] N. Verhoeckx, H. van den Elzen, F. Snijders and P. van Gerwen, “Digital echo cancellation
for baseband data transmission,” IEEE Trans. on Acoustics, Speech, and Signal Processing,
Vol.27, pp. 768-781, Dec 1979.
[3] Fan Hong and W. K. Jenkins, "An investigation of an adaptive IIR echo canceller: advantages and problems," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 12, pp. 1819-1834, Dec. 1988, doi: 10.1109/29.9027.
[4] A. F. Shalash, "Hybrid FIR-IIR Adaptive Echo Canceller for Wireline Applications," Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, 2005., 2005, pp. 364-368, doi: 10.1109/ACSSC.2005.1599769.
[5] Yen-Liang Chen, Cheng-Zhou Zhan and An-Yeu Wu, "Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system," 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 3150-3153, doi: 10.1109/ISCAS.2008.4542126.
[6] Diniz, P. S. R., Adaptive Filtering: Algorithms and Practical Implementations, Kluwer Academic Publishers, Boston, MA, Second Edition, 2002. ISBN 1-4020-7125-6.
[7] Simon Haykin, Adaptive Filter Theory : International Edition, 5th Edition, ISBN 027376408X
[8] B. Widrow, J. M. McCool, M. G. Larimore and C. R. Johnson, "Stationary and nonstationary learning characteristics of the LMS adaptive filter," in Proceedings of the IEEE, vol. 64, no. 8, pp. 1151-1162, Aug. 1976, doi: 10.1109/PROC.1976.10286.
[9] J. Ebrahimi, S. H. Hosseinian and G. B. Gharehpetian, "Unit Commitment Problem Solution Using Shuffled Frog Leaping Algorithm," in IEEE Transactions on Power Systems, vol. 26, no. 2, pp. 573-581, May 2011, doi: 10.1109/TPWRS.2010.2052639.
[10] Muzaffar Eusuff and Kevin Lansey, “Shuffled frog-leaping algorithm: a memetic meta-heuristic for discrete optimization,” Engineering optimization, vol. 38, no. 2, pp. 129-154, 2004.
[11] P. Luo, Q. Lu and Chenxi Wu, "Modified shuffled frog leaping algorithm based on new searching strategy," 2011 Seventh International Conference on Natural Computation, Shanghai, 2011, pp. 1346-1350, doi:10.1109/ICNC.2011.6022273.
[12] Jiménez-Galindo D, Casaseca-de-la-Higuera P, San-José-Revuelta LM (2019) A novel design method for digital FIR/IIR filters based on the shuffle frog-leaping algorithm. In: 2019 27th European signal processing conference (EUSIPCO), pp 1–5
[13] Katsuhiko Ogata, Discrete-Time Control Systems, ISBN 0-13-216227-X.
[14] Shao-Syun Huang, “A High Cost-Effective Echo Canceller Design for 2.5G/5GBASE-T Ethernet Transceiver,” Oct 2021.
指導教授 薛木添(Muh-Tian Shiue) 審核日期 2022-9-27
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