博碩士論文 108521063 詳細資訊




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姓名 顏玉家(Yu-Chia Yen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 運用改良粒子群最佳化演算法之近端串擾消除器電路設計
(Design of NEXT Canceller Circuit with Improved Particle Swarm Optimization Algorithm)
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摘要(中) 本論文根據IEEE 802.3bz™-2016規範標準[1],設計近端串擾消除器。近端串擾(Near-end crosstalk, NEXT)在雙絞線中得以抑制,但在不同對雙絞線中存在影響,在高速電路中對訊號品質有較高要求,因此近端串擾需要被解決。一般近端串擾消除器所使用的自適應濾波器為有限脈衝響應濾波器(Finite Impulse response filter, FIR filter),有結構簡單、演算法容易取得的特點,然而隨著近端串擾雜訊通道越長,有限脈衝響應濾波器為與之匹配,階數隨之增加,這使得成本大幅增加,故尋找替代結構成為重要的議題。本論文以無限脈衝響應濾波器(Infinite Impulse response filter, IIR filter)替代有限脈衝響應濾波器,運用其脈衝響應特性,無限脈衝響應濾波器可用較少的階數來模擬通道。自適應無限脈衝響應濾波器採用改良粒子群最佳化演算法,克服誤差平面存在多個局部最小值(Local minimum)問題,使其能收斂至全域最小值(Global minimum),並讓濾波器性能表現符合規範。在硬體實現上,以Verilog 撰寫電路並用NC-Verilog模擬,並透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能,最終由Design Compiler與IC Compiler以TSMC 40 nm製程來合成電路,並確認運作速度及功能符合規範。
摘要(英) This paper designs a near-end crosstalk canceller according to the IEEE 802.3bz™-2016 specification standard [1]. Near-end crosstalk (NEXT) can be suppressed in twisted pair, but it has influence on different pairs of twisted pair. In high-speed circuits, there is a higher requirement for signal quality, so near-end crosstalk needs to be solved. Generally, the adaptive filter used in the near-end crosstalk canceller is the finite impulse response filter (FIR filter), which has the characteristics of simple structure and easy algorithm. However, as the NEXT noise channel becomes longer, the order of the finite impulse response filter increases in order to match it, which increases the cost significantly.
In this paper, the infinite impulse response filter (IIR filter) is used to replace the finite impulse response filter. Using its impulse response properties, infinite impulse response filter can model channels with fewer orders. Adaptive infinite impulse response filter adopts an improved particle swarm optimization algorithm to overcome the problem of multiple local minima in the error plane, so that it can converge to the global minimum value and make the filter performance meet the specifications.
In hardware implementation, the circuit is written in Verilog and simulated with NC-Verilog, and the circuit function is verified through SMIMS VeriEnterprise Xilinx FPGA. Finally, Design Compiler and IC Compiler use TSMC 40 nm process to synthesize the circuit, and confirm that the operation speed and function meet the specifications.
關鍵字(中) ★ 近端串擾濾波器
★ 無限脈衝響應濾波器
★ 粒子群最佳化演算法
★ 改良粒子群最佳化演算法
★ 乙太網路
關鍵字(英) ★ NEXT canceller
★ IIR filter
★ Particle swarm optimization
★ Improved particle swarm optimization
★ Ethernet
論文目次 摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xiii
第一章 緒論 - 1 -
1.1背景 - 1 -
1.2 研究動機 - 1 -
1.3 論文貢獻 - 2 -
1.4論文架構 - 2 -
第二章 近端串擾消除器架構介紹 - 3 -
2.1有限脈衝響應電路架構 - 4 -
2.2無限脈衝響應電路架構 - 6 -
第三章 近端串擾消除器演算法介紹 - 8 -
3.1 粒子群最佳化(Particle Swarm Optimization, PSO)演算法 - 8 -
3.2具有差分擾動速度的粒子群最佳化(PSO-DV)演算法 - 11 -
3.2.1 差分進化(Differential evolution)演算法 - 11 -
3.2.2 具有差分擾動速度的粒子群最佳化(PSO-DV)演算法 - 12 -
3.3改良粒子群最佳化演算法 - 14 -
3.4多樣性 - 16 -
第四章 通道模型介紹 - 25 -
第五章 系統架構與模擬結果 - 30 -
5.1 系統架構 - 30 -
5.2 自適應濾波器 - 31 -
5.3 演算法 - 32 -
5.4 模擬環境 - 33 -
5.4.1 十公尺模擬環境 - 33 -
5.4.2 二十公尺模擬環境 - 33 -
5.4.3 三十公尺模擬環境 - 34 -
5.4.4 四十公尺模擬環境 - 34 -
5.4.5 五十公尺模擬環境 - 35 -
5.4.6 六十公尺模擬環境 - 35 -
5.4.7 七十公尺模擬環境 - 36 -
5.4.8 八十公尺模擬環境 - 36 -
5.4.9 九十公尺模擬環境 - 37 -
5.4.10 一百公尺模擬環境 - 37 -
5.5 成本函數 - 38 -
5.6 模擬結果 - 45 -
5.6.1 十公尺模擬結果 - 45 -
5.6.2 二十公尺模擬結果 - 46 -
5.6.3 三十公尺模擬結果 - 47 -
5.6.4 四十公尺模擬結果 - 48 -
5.6.5 五十公尺模擬結果 - 49 -
5.6.6 六十公尺模擬結果 - 50 -
5.6.7 七十公尺模擬結果 - 51 -
5.6.8 八十公尺模擬結果 - 52 -
5.6.9 九十公尺模擬結果 - 53 -
5.6.10 一百公尺模擬結果 - 54 -
5.6.11 全時間相位模擬結果 - 55 -
第六章 電路架構與晶片實現 - 60 -
6.1硬體設計規格 - 60 -
6.2 電路設計流程 - 61 -
6.3硬體電路介紹 - 62 -
6.3.1記憶體 - 62 -
6.3.2計算與更新單元 - 64 -
6.3.3無限脈衝響應濾波器 - 66 -
6.3.4平均絕對誤差 - 68 -
6.4模擬驗證 - 69 -
6.5晶片設計結果 - 72 -
第七章 結論與未來展望 - 81 -
參考文獻 - 82 -
參考文獻 [1] IEEE Standard for Ethernet Amendment 7: Media Access Control Parameters, Physical Layers, and Management Parameters for 2.5 Gb/s and 5 Gb/s Operation, Types 2.5GBASE-T and 5GBASE-T.
[2] J. Kennedy and R. Eberhart, "Particle swarm optimization," Proceedings of ICNN′95 - International Conference on Neural Networks, 1995.
[3] N. J. Fiege, “Multirate digital signal processing: multirate systems, filter banks, wavelets”, 1994.
[4] J.J. Shynk, "Adaptive IIR filtering, " IEEE ASSP Magazine, vol. 6, no. 2, pp. 4-21, April. 1989.
[5] Zhi-Hui Zhan, Jun Zhang, Yun Li, Yu-Hui Shi, "Orthogonal Learning Particle Swarm Optimization, " IEEE Trans. Evol. comput., vol. 15, no. 6, pp. 832-847, Dec. 2011.
[6] K. Vaisakh, M. Sridhar and K. S. L. Murthy, "Adaptive PSO-DV Algorithm for Minimization of Power Loss and Voltage Instability," 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009, pp. 140-144.
[7] S. Das, A. Abraham, A. Konar, Particle swarm optimization and differential evolution algorithms: technical analysis, applications and hybridization perspectives, in: Ying Liu et al. (Eds.), Advances of Computational Intelligence in Industrial Systems, Studies in Computational Intelligence, Springer Verlag, Germany, 2008, pp. 1-38.
[8] Storn R., Price K., “Differential evolution: A Simple and Efficient Adaptive Scheme for Global Optimization over Continuous Spaces,” Technical report,TR-95-012, International Computer Sciences Institute , 1995.
[9] Price K., “Differential Evolution vs. the functions of the ICEO,” Proceeding of 1997 IEEE International Conference on Evolutionary Computation, 1997.
[10] R. Ursem, “Diversity-Guided Evolutionary Algorithms,” Parallel Problem Solving from Nature — PPSN VII, pp. 462–471, 2002.
[11] S. Singh, A. Ashok, T. R. Rawat and M. Kumar, "Optimal IIR System Identification Using Flower Pollination Algorithm", IEEE First International Conference on Power Electronics Intelligent Control and Energy Systems, pp. 1-6, 2016.
[12] Y. Y. Chen, “Design and Integration of Equalizer, Echo Canceller and Timing Recovery Circuit for IEEE 802.3bp™-2016 Automotive Ethernet Transceiver,” Jan 2021.
[13] C. Y. Tsai, “Design of Adaptive Equalizer and Timing Recovery Circuit with Particle Swarm Optimization Algorithm,” Jun 2021.
指導教授 薛木添(Muh-Tian Shiue) 審核日期 2022-9-27
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