應用於第五代通訊之寬頻氮化鎵多悌功率放大 器暨有無使用類比預失真線性化電路之互補式 金氧半導體堆疊式功率放大器

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唐晟哲(Cheng-Che Tang) 查詢紙本館藏

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電機工程學系

論文名稱

應用於第五代通訊之寬頻氮化鎵多悌功率放大器暨有無使用類比預失真線性化電路之互補式金氧半導體堆疊式功率放大器
(A Broadband GaN Doherty Power Amplifier and CMOS Stacked-Power Amplifiers With/Without Analog Predistortion Linearizer for 5G Communications)

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摘要(中)

此篇論文利用穩懋半導體公司 (WINTM) 所提供之0.25-µm GaN/SiC 製程與台灣積體電路製造股份有限公司 (tsmcTM) 018-µm CMOS 製程分別設計應用於n79頻段之多悌功率放大器與基於變壓器之推挽式功率放大器、n77頻段之堆疊式功率放大器搭配線性化電路。
第二章使用多悌負載架構於GaN功率放大器之設計來改善功率回退處之功率附加效率。利用數學分析得到一寬頻負載調變網路，並在輸入匹配使用二階帶通濾波器。從量測結果可觀察到其3-dB頻寬為4.4-5.5 GHz，頻帶內最大傳輸增益為15.24 dB，大訊號量測數據因量測儀器之限制無法提供完整結果，量測到之最大輸出功率約為37.6 dBm，其功率附加效率約為25 %、最高功率回退之功率附加效率約為18 %，晶片面積為7.81 mm2 (2.74 mm×2.73 mm)。
第三章分成兩部份：第一部份使用0.18-µm CMOS於n79頻段之推挽式功率放大器，此設計採用基於變壓器之堆疊式架構，同時使用電阻式自偏壓與中和化方法減少電路不穩定性和複雜性。量測結果顯示在n79頻段內最大傳輸增益為17.4 dB，最大輸出功率約為24.06 dBm，1-dB增益壓縮點輸出功率為19.47 dBm，最高功率附加效率約為12.96 %，晶片面積為3.9 mm2 (3 mm×1.3 mm)。第二部份使用0.18-µm CMOS於n77~n79頻段之線性化堆疊式功率放大器，此設計輸出利用二階帶通濾波器達到二倍頻開路之效果，輸入使用變壓器達到隔絕直流與寬頻匹配，為了在不損失效率的前提下，改善其AM-AM之特性，在輸入串接一類比預失真電路。在輸出級堆疊式電晶體間加入一米勒電容以調整電晶體之輸入阻抗達到特性的最佳化，其操作頻寬包含n77~n79頻段為3.3-5 GHz，最大傳輸增益為24.54 dB，最大輸出功率約為24.91 dBm，最高功率附加效率約為30.4 %，1-dB增益壓縮點之輸出功率為23.45 dBm、功率附加效率約為25.3 %，晶片面積為2.1 mm2 (2.1 mm×1 mm)。

摘要(英)

This thesis proposed three power amplifiers (PAs) which were designed and fabricated in in WINTM 0.25-µm GaN/SiC and tsmcTM 0.18-µm CMOS technologies. The first PA is a GaN/SiC Doherty power amplifier (DPA) for n79-band applications. The second and third PAs were implemented by transformer-based push-pull and stacked topologies with linearizer for n79 and n77-band operations, respectively.
Chapter 2 describes a GaN DPA for power added efficiency (PAE) improvement at power back-off condition. According to the results of mathematical analysis, the broadband load-modulation networks and a second-order band-pass filter for input matching were derived. The measurements achieve a peak power gain of 15.24 dB across a 3-dB bandwidth from 4.4 to 5.5 GHz. Due to the measurement restrictions, large signal measurement cannot provide complete data. The results show a maximum saturation power (Psat) of 37.4 dBm with a 25 % of PAE, and PAE at back-off 6 dB of 18 % in n79 band. The chip area of the GaN die is 7.81 mm2 (2.74 mm×2.73 mm).
Chapter 3 consists of two parts, the first one is a design of the transformer-based push-pull power amplifier with stacked structure in tsmcTM 0.18-µm CMOS for n79-band. The neutralization and resistive self-biased techniques were adopted for the reduction of circuit unstability and complexity. The measurements achieve a peak power gain of 17.4 dB across n79-band. The large signal results show a maximum Psat of 24.06 dBm with a 12.96 % of PAE, and the output 1-dB gain-compression power (OP1dB) of 19.47 dBm in n79-band. The chip area of the CMOS die is 3.9 mm2 (3 mm×1.3 mm). The second one is a linear stacked power amplifier in tsmcTM 0.18-µm CMOS for n77~n79-band. A second-harmonic open circuit was realized with the use of a second-order bandpass filter. And a transformer was used in the input for DC-block and broadband matching. The power amplifier used an analog pre-distortion circuit to improve the AM-AM performance without cost of the efficiency. To optimize the performance of the power amplifier, a Miller capacitor was added in the output stage to fine-tune the input impedance of the stacked transistors. The measurements achieve a peak power gain of 24.54 dB across n77~n79-band. The large-signal results show a maximum Psat of 24.91 dBm with a 30.4 % of PAE, and the OP1dB of 23.45 dBm with a 25.3 % of PAE in n77~n79-band. The chip area of the CMOS die is 2.1 mm2 (2.1 mm×1.3 mm).

關鍵字(中)

★ 多悌
★ 堆疊式
★ 預失真
★ 功率放大器

關鍵字(英)

★ Doherty
★ stacked
★ pre-distortion
★ power amplifier

論文目次

摘要 i
Abstract iii
致謝 v
目錄 vii
圖目錄 ix
表目錄 xiii
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節簡介 2
第二章應用5G頻段之多悌氮化鎵功率放大器 3
2-1 研究現況 3
2-2 功率放大器簡介 5
2-3 多悌功率放大器介紹 8
2-4 應用於n79頻段氮化鎵之兩級多悌功率放大器 14
2-4-1 架構圖 14
2-4-2 電路圖 17
2-4-3 電晶體尺寸選擇 18
2-4-4 輸出匹配設計 21
2-4-5 功率分配器設計 30
2-4-6 輸入匹配設計與偏壓電阻之選擇 33
2-4-7 電路模擬與量測結果 39
2-4-8 結果比較與討論 51
第三章應用於5G頻段之堆疊式功率放大器 55
3-1 研究現況 55
3-2 堆疊式功率放大器介紹 58
3-3 磁耦合變壓器簡介 61
3-4 線性化結構簡介 66
3-4-1 Cold-FET 預失真線性化技術 66
3-4-2 基於包絡偵測器之預失真電路 69
3-5 應用於n79頻段之堆疊式功率放大器 72
3-5-1 電路圖 72
3-5-2 電晶體偏壓選擇與自偏壓方法 74
3-5-3 輸出匹配設計 76
3-5-4 級間與輸入變壓器設計 83
3-5-5 電路模擬與量測結果 88
3-5-6 結果比較與討論 102
3-6 應用於n77~n79頻段搭配預失真電路之堆疊式功率放大器 106
3-6-1 電路圖 106
3-6-2 電晶體偏壓選擇 108
3-6-3 輸出匹配設計 109
3-6-4 輸入匹配設計 113
3-6-5 電路模擬結果 117
3-6-6 結果比較與討論 124
第四章結論 126
4-1 總結 126
4-2 未來方向 127
參考文獻 129

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2022-8-26

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