博碩士論文 108521120 詳細資訊




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姓名 王致凱(Chih-Kai Wang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於 6-GHz 免執照頻段之 CMOS 注入鎖定除頻器之設計
(Design of CMOS Injection-Locked Frequency Divider for the 6-GHz Unlicensed Band)
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摘要(中) 無線網路(Wi-Fi)在二十一世紀初問世,然而在二十年間飛速發展到了 IEEE 802.11ax (Wi-Fi 6),美國 FCC 在 2020 年開放了在 6 GHz 附近(5.925-7.125 GHz)、頻寬達 1.2 GHz 的新頻段。可以支援 6-GHz 免執照的 Wi-Fi 標準稱為 Wi-Fi 6E,因此支援此頻段的無線收發機及其中的頻率合成器的開發皆有其必要。由於射頻電路飛速發展,操作頻率不斷提高,注入鎖定除頻器在頻率合成器中已有舉足輕重的地位。本架購所要應用是將壓控振盪器設計於兩倍的本地震盪頻率,後面接一個除以二的除頻器,除頻器輸出才是本地震盪訊號。在本論文中我們分析一個雙混頻技術直接注入鎖定除頻器,並且對其模擬與實作,最後下針得到量測結果。
注入鎖定除頻器主要分為尾端注入與直接注入兩類,由於直接注入的架構較容易達到寬頻的效果,所以目前被廣為應用,不過其架構為非對稱架構,於是我們參考一個對稱架構的除二注入鎖定除頻器,對其分析並實作。我們希望可以從此架構出發,透過每一種元件的特性,尋找本架構的特性及趨勢,便於日後的設計,在第二章,我們利用的雙混頻技術直接注入鎖定除頻器之電路架構,將電路做分析。首先從 TSMC 0.18-um CMOS 製程模型中的被動元件,中心抽頭電感的電感起頭,製程模型中的三種不同線寬的電感,全部都調整到幾個特定的感值,將感值跟 Q 值記錄下來方便做後續的分析。電感分析後,再做一個 LC-tank 交錯耦合振蕩器,並使用先前的電感規格模擬。我們從最小的能起振電晶體尺寸開始模擬,在逐漸將電晶體尺寸加大,收集模擬數據作圖。從振盪器到除頻器到除頻器,最後透過共振電感改善電路表現。我們從中發掘出每個架構中的元件的趨勢,還有對整體的影響,找到優化的方向。未來類似架構在高頻操作時可以利用傳輸線共振的方式設計並實現電路
在第三章中我們將本論文的 6-GHz 無執照頻段的雙混頻技術直接注入鎖定除頻器實作,目標為輸出頻段可以覆蓋在 5.925-7.125 GHz (輸入為 11.85-14.25 GHz)。本專題參考[1]中的除二架構,本架構優勢在於對稱架構與雙混頻技術(dual-mixing technique)。量測結果中鎖定頻寬為 11.0-15.6 GHz (35.4%),在我們所需的頻要(11.5-14.5 GHz)上輸出功率有大於 -5 dBm,直流功率消耗小於 3.9 mW,最後 FoM 為 9.07%/mW,與文獻中其他除二注入鎖定除頻器比較,有不錯的鎖定頻寬,表現中上。
本論文在最後第四章做總結,我們對本專題電路全面的分析,利用每個元件特性,尋找可改進的方向。最後透過共振電感,改善輸入端注入訊號流失的問題。下一章設計並實現了 6-GHz 無執照頻段的注入鎖定除頻器,並用實際量測結果與比較做結尾。
摘要(英) Wireless network (Wi-Fi) came out at the beginning of the 21st century. However, it has rapidly developed to IEEE 802.11ax (Wi-Fi 6) in the past two decades. The FCC in the United States has opened the area around 6 GHz (5.925-7.125 GHz) in 2020. A new frequency band with a bandwidth of 1.2 GHz. The Wi-Fi standard that can support 6-GHz license-free is called Wi-Fi 6E. Therefore, the development of wireless transceivers and frequency synthesizers supporting this frequency band is necessary. Due to the rapid development of radio frequency circuits and the continuous improvement of operating frequencies, injection-locked frequency dividers have already played a pivotal role in frequency synthesizers. The intended application of this rack purchase is to design the voltage-controlled oscillator at twice the frequency of the earthquake, followed by a frequency divider divided by two, and the output of the frequency divider is the signal of the earthquake. In this thesis, we analyze a dual-mixing technique that directly injects and locks the frequency divider, and simulates and implements it, and finally the needle is used to obtain the measurement result.
Injection-locked frequency dividers are mainly divided into tail injection and direct injection. Because the direct injection architecture is easier to achieve the effect of broadband, it is currently widely used, but its architecture is an asymmetric architecture, so we refer to a symmetric architecture The divide-by-two injection-locked frequency divider is analyzed and implemented. We hope that we can start from this architecture and look for the characteristics and trends of this architecture through the characteristics of each component, so as to facilitate future design. In Chapter 2, the dual-mixing technology we used directly injects into the circuit architecture of the locked frequency divider. The circuit is analyzed. First, start with the passive components in the TSMC 0.18-um CMOS process model and the inductance of the center-tapped inductor. The three inductors with different line widths in the process model are all adjusted to a few specific inductance values. The Q value is recorded to facilitate subsequent analysis. After the inductance analysis, make another LC-tank interleaved coupling oscillator and use the previous pole specifications to simulate. We started the simulation from the smallest possible transistor size, and gradually increased the size of the transistor, collecting simulation data for graphing. From the oscillator to the frequency divider to the frequency divider, finally the circuit performance is improved through the resonance inductance. We discovered the trend of the components in each architecture, as well as the overall impact, and found the direction of optimization. In the future, similar architectures can use transmission line resonance to design and implement circuits when operating at high frequencies.
In Chapter 3, we will directly inject the dual-mixing technology of the 6-GHz unlicensed frequency band of this paper into the locking divider. The goal is that the output frequency band can cover 5.925-7.125 GHz (the input is 11.85-14.25 GHz). This topic refers to the divide-by-two architecture in [1]. The advantage of this architecture lies in the symmetrical architecture and dual-mixing technique. In the measurement results, the locked bandwidth is 11.0-15.6 GHz (35.4 %), the output power is greater than -5 dBm at the required frequency (11.5-14.5 GHz), and the DC power consumption is less than 3.9 mW. Finally The FoM is 9.07%/mW. Compared with other divide-by-two injection-locked frequency dividers in the literature, it has a good locking bandwidth, and the performance is above-average.
This thesis concludes in the fourth chapter. We will make a comprehensive analysis of the circuit of this topic and use the characteristics of each component to find the direction that can be improved. Finally, through the resonance inductance, the problem of input signal loss at the input end is improved. The next chapter designs and implements an injection-locked divider for the 6-GHz unlicensed frequency band, and ends with actual measurement results and comparisons.
關鍵字(中) ★ 注入鎖定除頻器 關鍵字(英) ★ ILFD
論文目次 目錄
摘要 I
Abstract III
目錄 VII
圖目錄 IX
表目錄 IIIX
第一章 緒論 P.1
1.1研究動機 P.1
1.2文獻回顧 P.2
1.2.1除頻器文獻回顧 P.2
1.2.2注入鎖定除頻器文獻回顧 P.4
1.3論文架構 P.7
第二章 雙混頻技術直接注入鎖定除頻器之分析 P.9
2.1簡介 P.9
2.2直接注入鎖定除頻器之分析 P.10
2.2.1傳統直接注入鎖定除頻器 P.10
2.2.2雙混頻技術直接注入鎖定除頻器 P.12
2.3TSMC 0.18-μm CMOS 製程電感模型模擬 P.17
2.4 振盪器模擬 P.20
2.4.1振盪器相位雜訊對直流功率消耗作圖 P.22
2.4.2振盪器FoM對直流功率消耗作圖 P.26
2.5 除頻器模擬 P.30
2.5.1電感模型模型模擬 P.31
2.5.2除頻器鎖定頻寬對直流功率消耗作圖 P.34
2.5.3除頻器架構輸入與輸出模擬 P.40
2.5.4除頻器FoM對直流功率消耗作圖 P.43
2.6 除頻器改進模擬 P.45
2.7 結果與討論 P.51
第三章 雙混頻技術直接注入鎖定除頻器之實作 P.53
3.1簡介 P.53
3.2電路架構 P.54
3.3電路模擬與實測 P.57
3.3.1電路設計與模擬 P.57
3.3.2電路布局 P.64
3.3.3 量測結果 P.67
3.4結果與討論 P.69
第四章 結論 P.71
4.0.1未來展望 P.72
參考文獻 P.73
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[15] H. Zheng and H.-C. Luong, “Ultra-low-voltage 20-GHz frequency dividers using transformer feedback in 0.18-µm CMOS process,” IEEE Journal of Solid-State
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[16] S. Jang, R. Yang, C. Chang, and M. Juang, “Multi-modulus LC injection-locked frequency dividers using single-ended injection,” IEEE Microwave and Wireless
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[17] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda, “20-GHz quadrature injection-locked LC dividers with enhanced locking range,”
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指導教授 傅家相(Jia-Shiang Fu) 審核日期 2021-10-15
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