基於十六奈米鰭式場效電晶體平台實現通道轟擊電離編程機制之低成本高速嵌入式動態隨機存取記憶體

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姓名

黃誠楓(Cheng-Feng Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於十六奈米鰭式場效電晶體平台實現通道轟擊電離編程機制之低成本高速嵌入式動態隨機存取記憶體
(A Low-cost and High-speed Memory-array of Embedded DRAM by Channel-impact-ionization (CII) Program-scheme in 16 nm FinFET Platform)

相關論文

★ 具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現

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至系統瀏覽論文 (2027-10-21以後開放)

摘要(中)

隨著科技的進步，5G建設、人工智慧（AI）、車用電子、物聯網 (Internet of Things , IoT)等領域發展迅速且滲透至生活各個層面中。越快速的資料傳輸和更龐大的系統對記憶體的效能與需求日益增加。如何設計出能夠符合現今強調寬廣頻寬與低延遲的要求，且能夠廣泛應用於各種層面的記憶體晶片將會是未來記憶體發展的一大趨勢。
在本論文中，提出了創新的1T-1T的embedded DRAM架構，其中1T作為控制電晶體另一個1T則為儲存電荷的儲存電晶體，此設計所採用的編程機制為碰撞游離效應 (impact ionization)，利用impact ionization機制產生的電子電洞對中的電子大量在nMOSFET的通道內累積，再搭配儲存電晶體的閘極浮節來達到儲存電荷的目的。藉由使用16 nm FinFET製程製作的embedded DRAM可以有效縮減傳統DRAM 1T-1C的電容所帶來的龐大面積，也同時降低了晶片的操作電壓來達到低功耗的效果。
本研究設計容量為4kb的embedded DRAM矩陣單位面積僅有0.07 μm2，晶片面積為0.214 μm2，且單元記憶胞 (unit cell) 的良率超過99 %，具有小面積、高良率與低成本的優勢。記憶體矩陣與其周邊電路具有很快的編程與讀取速度 (7 ns)，同時具有很低的操作電壓 (0.8 V)、良好的資料保存性 (120 µsec) 與優秀的抗干擾性，在連續進行超過1013操作後仍然可以正常運作且可以在75 ℃的高溫下操作展現出良好的可靠度與耐久性。在進行讀取時，僅需要使用-0.2 V的電壓來對儲存電晶體進行讀取便可以有超過30倍的0/1讀取窗口，且僅有36 nW的讀取消耗功率。在上述的特性中顯示本設計之1T-1T的embedded DRAM在許多層面皆有相當好的表現，在未來將會有很好的整合性，也會有更多且靈活的應用層面，也可以幫助embedded DRAM隨著FinFET製程繼續微縮到5~3 nm，在未來將可有效突破目前電晶體製程與嵌入式記憶體整合應用之瓶頸。

摘要(英)

With advancement of science and technology, the 5th generation mobile networks (5G), artificial intelligence (AI), automotive electronics, internet of things (IoT) have developed rapidly and could be active in all aspects. Owing to faster data transfers and bigger systems, demands on memory performance and needs are also increasing. How to design a memory chip that can meet requirements of today′s emphasis on wide bandwidth and low latency widely used in various levels will be a development tendency of memory in the future.
In this thesis, an innovative 1T-1T embedded DRAM architecture is proposed, in which 1T is used as a control transistor and the other 1T is a storage transistor that stores charges. Programming mechanism used in this design is impact ionization, many electrons in the electron-hole pair generated by the impact ionization mechanism are accumulated in the channel of the nMOSFET, and with the storage transistor gate floating the charges will be stored. The embedded DRAM fabricated by using the 16 nm FinFET process can effectively reduce huge area caused by capacitance of the traditional 1T-1C DRAM and at the same time reduce the operating voltage to achieve low-power consumption.
In design of this test chip, the 1T-1T embedded DRAM 4kb array unit cell has area of only 0.07 μm2 and the chip area of 0.214 mm2, and yield of the unit cell exceeds 99%, which has advantages of small area, high-yield and low cost. The memory array and its peripheral circuits have fast programming and reading speeds, low operating voltage, high data retention and excellent anti-interference performance. This memory can be operated at a high temperature of 75 °C and after more than 1013 continuous operations. These shows good reliability and durability. During reading the unit cell, just a voltage of -0.2 V applied to the storage transistor can have more than 30 times of 0/1 reading window with only 36 nW of reading power consumption. The 1T-1T embedded DRAM of this design has magnificent performance in many aspects. In the future, this embeddded DRAM technology can be extensively deployed in mobile and portable electronic devices with good cost-efficiecny and ultra-low power-consumption and can also shrink to 5~3 nm FinFET process to effectively break through the bottleneck of integrated application of transistor process and embedded memory.

關鍵字(中)

★ 動態隨機存取記憶體
★ 嵌入式動態隨機存取記憶體
★ 記憶體矩陣
★ 記憶體單元

關鍵字(英)

★ Dynamic-Random Access Memory (DRAM)
★ embedded Dynamic-Random Access Memory (eDRAM)
★ memory array
★ memory cell

論文目次

摘要 I
Abstract II
致謝 IV
圖目錄 VII
表目錄 IIX
一、導論 1
1.1背景 1
1.2研究動機 3
1.3論文架構 4
二、The Unit Cell of 4Kb 1T-1T embedded DRAM Array 8
2.1 DRAM 和embedded DRAM 介紹 8
2.1.1 動態隨機存取記憶體 (DRAM) 介紹 8
2.1.2 嵌入式動態隨機存取記憶體 (eDRAM) 介紹 9
2.2 傳統 DRAM 可靠度問題 10
2.3 DRAM和embedded DRAM 應用 10
2.4 碰撞游離效應 (Impact Ionization) 11
2.5 實驗設置 12
三、Circuit Level of 4Kb 1T-1T embedded DRAM Array 16
3.1介紹 16
3.2 Unit Cell 結構 17
3.3 操作條件 18
3.4 4Kb 1T-1T embedded DRAM 矩陣架構 19
3.5 電壓感測放大器 20
3.6 邏輯控制開關電路 21
3.7 正電壓位準偏移器 (Positive Level Shifter) 22
3.8 高速負電壓位準偏移器 (High-Speed Negative Level Shifter) 23
四、實驗結果 39
4.1 編程與讀取Shmoo圖 (Program/Read Shmoo Plot) 39
4.2 Unit Cell良率 (Bit Yield) 40
4.3 讀取電流分布 (Current Distribution) 40
4.4 資料保存時間 (Retention Time) 41
4.5 耐久度測試 (Endurance) 42
4.6 資料擾動測試 (Data Disturbrance) 43
4.7 記憶體輸出資料量測 (Output Data) 44
五、結論 59
參考文獻 64

參考文獻

[1] N. Gupta, A. Makosiej, H. Shrimali, A. Amara, A. Vladimirescu and C. Anghel, "Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM," in IEEE Transactions on Nanotechnology, vol. 20, pp. 270-277, 2021, doi: 10.1109/TNANO.2021.3061607.
[2] W. Choi, G. Kang, and J. Park, “A refresh-less eDRAM macro with embedded voltage reference and selective read for an area and power efficient Viterbi decoder,” IEEE J. Solid-State Circuits, vol. 50, no. 10, pp. 2451–2462, Oct. 2015.
[3] E. Yoshida and T. Tanaka, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory," in IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 692-697, April 2006
[4] S. Ramaswamy and M. J. Kumar, "Junctionless Impact Ionization MOS: Proposal and Investigation," in IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4295-4298, Dec. 2014, doi: 10.1109/TED.2014.2361343.
[5] Song Zhao et al., "GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design," International Conference on Simulation of Semiconductor Processes and Devices, 2002, pp. 43-46, doi: 10.1109/SISPAD.2002.1034512.
[6] Churoo Park et al., "A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques," Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 2005, pp. 370-373, doi: 10.1109/VLSIC.2005.1469407.
[7] S. Shim et al., "A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 212-214, doi: 10.1109/ISSCC.2018.8310259.
[8] D. Kim et al., "A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx," in IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 167-177, Jan. 2020, doi: 10.1109/JSSC.2019.2948806.
[9] M. J. Kramer, E. Janssen, K. Doris and B. Murmann, "A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2891-2900, Dec. 2015, doi: 10.1109/JSSC.2015.2463110.
[10] J. -A. Wang, Y. -Y. Zhao and Z. -P. Zhang, "A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 9, pp. 1524-1528, Sept. 2020, doi: 10.1109/TCSII.2020.3012150.
[11] X. Chen, Y. Li and T. Zhang, "Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs)," in IEEE Transactions on Computers, vol. 68, no. 3, pp. 426-439, 1 March 2019, doi: 10.1109/TC.2018.2871683.
[12] J. Song et al., "A 3T eDRAM In-Memory Physically Unclonable Function With Spatial Majority Voting Stabilization," in IEEE Solid-State Circuits Letters, vol. 5, pp. 58-61, 2022, doi: 10.1109/LSSC.2022.3158630.
[13] H. Shin, J. Sim, D. Lee and L. -S. Kim, "A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks," 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019, pp. 1-8, doi: 10.1109/ICCAD45719.2019.8942072.
[14] J. H. Ahn, J. Leverich, R. Schreiber and N. P. Jouppi, "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs," in IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 5-8, Jan. 2009, doi: 10.1109/L-CA.2008.13.
[15] Y. Kim et al., "A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 204-206, doi: 10.1109/ISSCC.2018.8310255.
[16] K. Hwang et al., "A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 210-212, doi: 10.1109/ISSCC.2018.8310258.
[17] C. H. Tan, J. S. Ng, G. J. Rees and J. P. R. David, "Statistics of Avalanche Current Buildup Time in Single-Photon Avalanche Diodes," in IEEE Journal of Selected Topics in Quantum Electronics, vol. 13, no. 4, pp. 906-910, July-aug. 2007, doi: 10.1109/JSTQE.2007.903843.
[18] J. -H. Park, J. -S. Song, S. -I. Lim and S. Kim, "A high speed and low power 4∶1 multiplexer with cascoded clock control," 2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010, pp. 316-319, doi: 10.1109/APCCAS.2010.5774935.
[19] S. M. Kim, T. W. Oh and S. -O. Jung, "Sensing voltage compensation circuit for low-power dram bit-line sense amplifier," 2018 International Conference on Electronics, Information, and Communication (ICEIC), 2018, pp. 1-4, doi: 10.23919/ELINFOCOM.2018.8330545.
[20] R. Sinha, M. S. Hashmi and G. A. Kumar, "A positive level shifter for high speed symmetric switching in flash memories," 18th International Symposium on VLSI Design and Test, 2014, pp. 1-5, doi: 10.1109/ISVDAT.2014.6881064.
[21] P. Liu, X. Wang, D. Wu, Z. Zhang and L. Pan, "A novel high-speed and low-power negative voltage level shifter for low voltage applications," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 601-604, doi: 10.1109/ISCAS.2010.5537521.
[22] S. M. Kim, B. Song, T. W. Oh and S. -O. Jung, "Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM," 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2018, pp. 65-68, doi: 10.1109/PRIME.2018.8430359.
[23] T. -J. Lee, W. -J. Su, L. K. S. Tolentino and C. -C. Wang, "A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment," 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), 2021, pp. 153-156, doi: 10.1109/APCCAS51387.2021.9687736.
[24] B. N. Bagamma, K. S. V. Patel and P. Ravi, "Implementation of 5–32 address decoders for SRAM memory in 180nm technology," 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), 2017, pp. 110-114, doi: 10.1109/ICEECCOT.2017.8284649.
[25] D. Berwal, A. Kumar and Y. Kumar, "Low power conditional pulse control with Transmission Gate Flip-Flop," International Conference on Computing, Communication & Automation, 2015, pp. 1358-1362, doi: 10.1109/CCAA.2015.7148589.
[26] N. Borrel et al., "Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation," 2015 IEEE International Reliability Physics Symposium, 2015, pp. FA.1.1-FA.1.6, doi: 10.1109/IRPS.2015.7112799.
[27] K. Baker and J. Van Beers, "Shmoo plotting: the black art of IC testing," in IEEE Design & Test of Computers, vol. 14, no. 3, pp. 90-97, July-Sept. 1997, doi: 10.1109/54.606005.
[28] S. Lyu and Z. Shi, "On-Chip Process Variation Sensor Based on Sub-Threshold Leakage Current with Weak Bias Voltages," 2019 International Conference on IC Design and Technology (ICICDT), 2019, pp. 1-4, doi: 10.1109/ICICDT.2019.8790891.
[29] T. Tomimatsu, T. Yamaguchi, M. Mizuo, T. Yamashita, Y. Kawasaki and A. Ishii, "Influence of STI stress on leakage current in buried P-N junction," 2013 13th International Workshop on Junction Technology (IWJT), 2013, pp. 107-108, doi: 10.1109/IWJT.2013.6644517.
[30] T. Ishida, T. Mine, D. Hisamoto, Y. Shimamoto and R. -i. Yamada, "Electron-Trap and Hole-Trap Distributions in Metal/Oxide/Nitride/Oxide/Silicon Structures," in IEEE Transactions on Electron Devices, vol. 60, no. 2, pp. 863-869, Feb. 2013, doi: 10.1109/TED.2012.2235145.
[31] W. Choi, G. Kang, and J. Park, “A refresh-less eDRAM macro with embedded voltage reference and selective read for an area and power efficient Viterbi decoder,” IEEE J. Solid-State Circuits, vol. 50, no. 10, pp. 2451–2462, Oct. 2015.
[32] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg, and A. Teman, “An 800-MHz mixed- VT 4T IFGC embedded DRAM in 28-nm CMOS bulk process for approximate storage applications,” IEEE J. Solid-State Circuits, vol. 53, no. 7, pp. 2136–2148, Jul. 2018.
[33] R. Giterman, A. Shalom, A. Burg, A. Fish and A. Teman, "A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET," in IEEE Solid-State Circuits Letters, vol. 3, pp. 110-113, 2020, doi: 10.1109/LSSC.2020.3006496.
[34] K. C. Chun, P. Jain, J. H. Lee and C. H. Kim, "A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias," 2009 Symposium on VLSI Circuits, 2009, pp. 134-135.
[35] D. Somasekhar et al., "2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, pp. 274-613, doi: 10.1109/ISSCC.2008.4523163.
[36] R. Saligram, S. Datta and A. Raychowdhury, "CryoMem: A 4–300-K 1.3-GHz Hybrid 2T-Gain-Cell-Based eDRAM Macro in 28-nm Logic Process for Cryogenic Applications," in IEEE Solid-State Circuits Letters, vol. 4, pp. 194-197, 2021, doi: 10.1109/LSSC.2021.3123866.
[37] R. Giterman, A. Teman and P. Meinerzhagen, "Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 12, pp. 1362-1366, Dec. 2017, doi: 10.1109/TCSII.2017.2768102.
[38] O. Maltabashi, H. Marinberg, R. Giterman and A. Teman, "A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8351360.
[39] K. C. Chun, P. Jain, J. H. Lee and C. H. Kim, "A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches," in IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1495-1505, June 2011, doi: 10.1109/JSSC.2011.2128150.
[40] F. Hamzaoglu et al., "A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 150-157, Jan. 2015, doi: 10.1109/JSSC.2014.2353793.

指導教授

謝易叡張孟凡(Eray Hsieh Meng-Fan Chang)

審核日期

2022-10-25

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