應用自差分電路對具有不同擊穿電壓之多層累增層的砷化銦鎵/砷化銦鋁之單光子雪崩二極體性能影響

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姓名	張筠萱(Yun-Hsuan Chang) 查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用自差分電路對具有不同擊穿電壓之多層累增層的砷化銦鎵/砷化銦鋁之單光子雪崩二極體性能影響 (Effect of self-differencing circuit on InGaAs/InAlAs single photon avalanche diodes of multiple multiplication layers with different punch through voltages)
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摘要(中)	單光子雪崩二極體(Single-photon Avalanche Diode, SPAD)在許多科學和工業領域都有很重要的地位，像是量子密鑰(Quantum Key Distribution)、自駕車的光達系統 (Light Detection And Ranging, LiDAR) 抑或是3D影像技術等等。以光纖通訊為主的光量子通訊應用需要一能偵測近紅外光波段之高靈敏度感測器，因此本文著眼於開發以砷化銦鎵為基礎的單光子崩潰二極體；然而，III-V材料的元件於磊晶時會產生許多缺陷，進而造成元件嚴重的後脈衝及暗計數問題。以砷化鋁銦 (InAlAs)作為累增層具有較高的崩潰機率，因此預期能有較高的單光子偵測效率 (single photon detection efficiency, SPDE)，故本論文以砷化銦鎵/砷化鋁銦單光子崩潰二極體進行元件特性探討。本論文中，我們所使用的單光子崩潰二極體具有三層累增層，相較於之前的磊晶設計，此次磊晶增加累增層厚度，也預期降低穿隧電流，同時增加載子崩潰的機率，然而這種設計改動，可能也會增加載子在能階中被缺陷捕獲的機率，進而會使後脈衝效應 (afterpulsing effect)與時基誤差 (timing jitter)變差，所以在累增層中間同樣加入額外電荷層來過渡電場強度，盡可能讓崩潰區域縮小，來改善前者帶來的afterpulsing 與timing jitter。本文比較三種不同擊穿電壓之元件，做完整的單光子特性討論，並且比較有無自差分電路達到電容消除對元件特性參數的影響。由量測結果發現三元件之崩潰電壓差異不大、但擊穿電壓有極大差異分別為9 V、16 V及30 V。元件以被動閘控模式(Passively Gated mode)操作以降低後脈衝效應，閘壓頻率依照有無自差分電路分別設定在9.9 MHz與10 kHz，隨著溫度下降，暗計數具有較明顯的溫度依賴性，在溫度200 K下也有較高的單光子偵測效率(~64 %)，三元件之間有相近的後脈衝機率，且時基誤差在不同溫度下有相近的結果；此外，我們亦比較有無自差分電路對元件特性表現之影響，結果顯示有自差分電路可有效改善暗計數，低溫時能有更高的單光子偵測效率，然而在室溫下，因為暗計數高，自差分方法反而會把接連兩個發生崩潰的訊號減除，限制了計數率，故無法量測到更高的單光子偵測效率。
摘要(英)	Single-photon Avalanche Diodes (SPADs) are important in many fields of science and industry, such as quantum key distribution, light detection and ranging (LiDAR) for self-driving cars, and also 3D imaging technology, etc. Especially, a very sensitive photon detector is highly demanded in the fiber-based photonic quantum communication. Therefore, we focus on the development of InGaAs-based SPAD for near infrared light detection. However, there are lots of defects during the epitaxy of III-V materials, which will cause serious afterpulsing effect and dark count problems. Since InAlAs exhibits high avalanche probability and hence high single photon detection efficiency (SPDE), we put our focus on the study of InGaAs/InAlAs SPADs. In this thesis, we present a comprehensive investigation on the InGaAs/InAlAs SPADs with triple multiplication layer. Compared with the previous structure design of dual multiplication layers, the increase in the thickness of the multiplication layer is also expected to reduce the effect of tunneling current and increase the probability of avalanche. However, this design may increase the probability of afterpulsing effect and degrade the timing jitter. Therefore, we propose a novel design in the multiplication layer - an additional charge layer. It can divide the multiplication layer into high electric field and sub-high electric field region, so that the avalanche breakdown region can be restricted within a smaller area. The figure of merits (FoM) of single photon detector for three mesa-type SPADs with different punch through voltage are studied. Those three SPADs have almost the same breakdown voltage but very different punch through voltage of 9V, 16V and 30V. We also compare FoMs of SPAD for the cases with and without the inclusion of self-differencing circuit. SPADs were operated by a passively gated mode circuit. Depending on whether or not to use the SD circuit, the operating frequency is set at 9.9 MHz or 10 kHz with the pulse width of 1.5 ns. With reducing the temperature, the dark count rate (DCR) can be effectively suppressed for dual mesa device. It also exhibits higher SPDE of 64 % at 200 K .There is no much difference in the timing jitter and also afterpulsing for all three devices. Besides, we further discuss the impact of incorporation of SD circuit on the device performance. It turns out that the DCR can be greatly suppressed with SD circuit, which improves the SPDE at lower temperature. However, because the DCR is high at room temperature, the detector can be blinded while there are two consecutive avalanche events, which restricts the count rate so as to draw a limit on the SPDE performance at room temperature.
關鍵字(中)	★ 單光子雪崩二極體 ★ 暗計數 ★ 時基誤差 ★ 單光子偵測效率 ★ 自差分電路	關鍵字(英)	★ SPAD ★ Dark count rate ★ Jitter ★ SPDE ★ SD-circuit
論文目次	中文摘要 i Abstract iii 目錄 v 圖目錄 vii 表目錄 ix 一、前言 1 1.1研究背景 1 1.2研究目的 6 二、基本原理及文獻探討 7 2.1 SPAD 基本元件物裡 7 2.1.1 I-V 特性操作原理 7 2.1.2二極體崩潰機制 8 2.2光子數目解析偵測器 10 2.2.1自差分電路 10 2.2.2光學自差分技術 11 2.2.3諧波減法技術 12 2.3元件參數介紹 13 2.3.1 暗計數 (dark count rate ) 13 2.3.2單光子偵測效率 (single photon detection efficiency) 15 2.3.3時基誤差 (timing jitter) 16 2.3.4響應率 (responsivity) 17 2.4元件操作截止電路 18 2.4.1自由運作電路 (free running mode circuit) 18 2.4.2閘控模式 (gated mode) 19 2.4.3 自我截止電路 (self-quchening ) 20 三、元件結構設計 22 3.1 SACGM 結構介紹 22 3.2元介磊晶設計 23 3.3元件模擬與設計 25 四、量測架構 27 4.1 降溫系統架設 27 4.2電壓電流量測 28 4.3暗計數量測方式 29 4.4光計數量測方式 31 4.5後脈衝及時基誤差量測方式 33 五、量測結果 36 5.1室溫下的電壓與電流量測結果 36 5.2變溫下的量測結果 39 5.2.1變溫下的電壓與電流量測結果 39 5.2.2變溫下暗計數量測 44 5.2.3 變溫下光計數量測 48 5.2.4 後脈衝機率量測 54 5.2.5 時基誤差量測 55 六、結論與未來展望 57 6.1結果比較與討論 57 6.2未來展望 58 參考文獻 59
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指導教授	李依珊許晉瑋(Yi-Shan Lee Jin-Wei Shi)	審核日期	2022-11-3
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博碩士論文 109521049 詳細資訊