博碩士論文 109552016 詳細資訊




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姓名 曾釋弘(Shih-Hung Tseng)  查詢紙本館藏   畢業系所 資訊工程學系在職專班
論文名稱 開啟製程相似檢查方法在組裝超級塊上以最小化額外的寫入延遲
(Enable Process Similarity Check Method on Grouping Super Block to Minimize the Extra Write Latency)
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摘要(中) 3D NAND閃存已成為數據存儲設備最流行的介質,並不斷擴大其市場和SSD等各種高速數據訪問需求領域的應用。為了最大化數據吞吐量,採用了NAND flash芯片內部不同平面的數據塊(block)和不同通道的NAND flash芯片並行訪問的概念,稱為超級塊(super block)。一個成功的超級塊訪問需要所有數據塊一起完成它們的工作才能完成操作。但是,這裡提出了額外延遲的問題。因為,即使在同一個 NAND 閃存芯片中,由於 NAND 閃存製造工藝,這些塊也會出現不同的特性和延遲。如果將最快和最慢的塊組裝到同一個超級塊中,則額外的延遲會顯著影響寫入性能。本研究提出了一種考慮塊之間製程相似性(process similarity)的超級塊組裝方法,通過創建、識別塊的“特徵序列(eigen-sequence)”來組裝最相似的塊,以減少超級塊的額外延遲。此外,這種方法允許我們有選擇地組裝一個快速或慢速的額外延遲減少的超級塊。根據寫入需求的不同優先級,上層可以為需求分配相應速度等級的超級塊,從而進一步提升寫入性能。
摘要(英) The 3D NAND flash memory has become the most popular media for data storage devices, and it keeps expanding its market and applications like SSD for various high-speed data access demand fields. In order to maximize the data throughput, the concept of parallel access of data block in different planes inside the NAND flash chip and NAND flash chips in different channels is employed, which is called a super block. A successful super block accessing needs all the blocks finish their works together to complete the operation. However, the problem of extra latency is raised here. Because, even in the same NAND flash chip, the blocks appear different characteristics and latency with one another due to NAND flash fabrication processes. If the fastest and slowest blocks are assembled into the same super block, the extra latency conspicuously influences the write performance. This study presents a super block assembly method considering of process similarity between blocks by creating, identifying the ”eigen-sequence” of blocks for the assembly of most similar blocks to reduce the extra latency for super blocks. In addition, this method allows us selectively assemble a fast or slow of extra latency reduced super block. Depending on the different priority of write demand, the upper level can assign the super block with an appropriated speed class to the demand, and therefore further enhance the write performance.
關鍵字(中) ★ 3D NAND快閃記憶體
★ 製程相似
★ 超級塊
★ 額外寫入延遲
關鍵字(英) ★ 3D NAND Flash Memory
★ Process Similarity
★ Super Block
★ Extra Write Latency
論文目次 摘要 i
Abstract ii
目錄 List of Tables iii
表目錄 List of Figures v
圖目錄 vi
I. Introduction - 1 -
II. Background - 6 -
2-1 SSD Organization - 6 -
2-2 3D NAND Flash Memory Organization - 7 -
2-3 The Process Similarity of 3D NAND - 11 -
III. Motivation - 13 -
IV. Characterizations - 17 -
4-1 The Process Similarity of 3D NAND - 19 -
4-1-1 Random Assembly - 19 -
4-1-2 Sequential Assembly - 20 -
4-1-3 Erase Latency Assembly - 20 -
4-1-4 Program Latency Assembly - 21 -
4-1-5 OPTIMAL ASSEMBLY @LOCAL(8) - 21 -
4-1-6 LWL-RANK ASSEMBLY @LOCAL(8) - 22 -
4-1-7 PWL-RANK ASSEMBLY @LOCAL(8) - 24 -
4-1-8 STR-RANK ASSEMBLY @LOCAL(1, 2, 4, 6, 8) - 25 -
4-1-9 STR-MEDIAN ASSEMBLY @LOCAL(4) - 25 -
4-2 Characterization Results - 26 -
4-2-1 Local Window Length = 4, Is the Balance Point - 27 -
4-2-2 STR-Based Method Reduces Extra PGM Latency Better - 28 -
4-2-3 Super Word-Line Extra PGM Latency Is Improved - 32 -
4-2-4 Super Block Erase Latency Is Benefited As Well - 34 -
4-2-5 Super Blocks Are In the Latency Order - 35 -
V. Method - 38 -
5-1 Process Similarity Check - 39 -
5-1-1 Update Block Parameters During Programming - 39 -
5-1-2 Assemble Super Block On Demand - 41 -
5-2 Diversion Performance Write - 43 -
VI. Evaluation - 47 -
6-1 Process Similarity Check - 47 -
6-2 Evaluation Result - 48 -
VII. Conclusion - 53 -
參考文獻 - 54 -
參考文獻 [1] Yu Cai, Saugata Ghose, Erich F. Haratsch, et al., ”Error Characterization, Mitigation, and Recovery in Flash-Memory Based Solid-State Drives”, pp. 1666-1704, Vol. 105, No. 9+, September 2017, Proceedings of the IEEE.
[2] Wonyoung Lee, Mincheol Kang, Seokin Hong, et al., ”Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages”, pp. 2033-2045, Vol. 27, No. 9, Septemer 2019, IEEE Transctions On VLSI Systems.
[3] Yixin Luo, Saugata Ghose, Yu Cai, et al., ”Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation”, pp 1–48, Article No.: 37, Issue 3, Volume 2, December 2018, Proceedings of the ACM on Measurement and Analysis of Computing Systems
[4] Yu Cai, Yixin Luo, Saugata, et al., ”Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery”, in DSN 2015
[5] Youngseop Shim, Myungsuk Kim, Myoungjun Chun, et al., ”Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs”, in MICRO 2019.
[6] Qiao Li, Min Ye, Yufei Cui, et al., ”Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash”, in MICRO 2020.
[7] Yu Cai, Saugata Ghose, Yixin Luo, et al., ”Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming”, in HPCA 2017.
[8] Congming Gao, Min Ye, Qiao Li, et al., ”Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory”, in MICRO 2019.
[9] Wei-Lin Wang, Tseng-Yi Chen, Yuan-Hao Chang, et al., ”How to Cut Out Expired Data with Nearly Zero Overhead for Solid-State Drives”, in DAC 2020.
[10] Wei-Lin Wang, Tseng-Yi Chen, Yuan-Hao Chang, et al., ”P-Alloc: Process-Variation Tolerant Reliability Management for 3D Charge-Trapping Flash Memory”, pp 1–19, Article No.: 142, Issue 5s, Vol. 16, October 2017, ACM Transactions on Embedded Computing Systems.
[11] Shunzhuo Wang, Fei Wu, Chengmo Yang, et al., ”WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime”, in DAC 2019.
[12] Yu Cai, Yixin Luo, Erich F. Haratsch, et al., ”Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory”, in HPCA 2015.
[13] Jiangpeng Li, Kai Zhao, Xuebin Zhang, et al., ”How Much Can Data Compressibility Help to Improve NAND Flash Memory Life-time?”, in FAST 2015.
指導教授 陳增益(Tseng-Yi Chen) 審核日期 2022-7-4
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