多阻態存取1T1R電阻式記憶體矩陣晶片的三態內容定址記憶體的設計和實現

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蘇煥翔(Huan-Hsiang Su) 查詢紙本館藏

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電機工程學系

論文名稱

多阻態存取1T1R電阻式記憶體矩陣晶片的三態內容定址記憶體的設計和實現
(Design and Implementation A Multi-level per-bit 1T1R Resistive Memory-based Ternary Content Addressable Memories)

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至系統瀏覽論文 (2028-12-20以後開放)

摘要(中)

隨著人工智慧(AI)發展，強調記憶體大容量與低功耗已經成為晶片設計的主流。為了達到記憶體大容量與低功耗的功能，在非揮發性記憶體中，快閃記憶體(FLASH)為主流，因為它擁有低成本低功耗的特性，但是讀寫速度較慢，近幾年隨著前瞻性記憶體技術快速發展(MRAM、FRAM、RRAM)，相對於FLASH有較快讀寫能力與耐久性，其中以RRAM較小面積低功耗與製程簡單最為有發展性。
在本論文中，提出利用RRAM 1T1R array架構實現一種多位元(multi-bit)儲存方式，1T1R中1T電晶體(control transistor)為用來控制RRAM cell控制電荷開關，1R為金屬-金屬氧化層-金屬(MIM)的結構。利用連續線性漸進調變(gradual tuning)的方法操作SET跟RESET，可以有效地使得MULTI-BIT-STORAGE多位元的窗口擴展更開，也同時代表本設計的RRAM不論在低阻態(Low-Resistance state)或是高阻態(High-Resistance state)都可以達到多位元的儲存方式。這也有利於實現三態內容定址記憶體(Ternary Content Addressable Memories ，TCAM)的操作，因為TCAM需要儲存三種狀態，也就是所謂的邏輯”1”、邏輯”0”以及”don’t care”，我們將低阻態(Low Resistance State, LRS)定義為邏輯”1”，高阻態(High Resistance State, HRS)定義為邏輯”0”，我們只需要在LRS以及HRS之間再找一個穩定的阻態來定義”don’t care”就可以實現TCAM的操作。
與傳統基於SRAM所實現的TCAM相比，本設計容量為1-Mb1Mb的RRAM矩陣的記憶胞單位面積約為0.0079 um2，，在面積上RRAM小了許多，並且在低阻態與高阻態最多可以達到接近200倍的差距，在多位元儲存的表現中，低阻態(Low-Resistance state)可以儲存10種狀態，高阻態(High-Resistance state)可以儲存15種狀態，總共可以儲存25狀態，可以有效的提升傳統SRAM所做的TCAM儲存密度低的問題，在功耗上，RRAM在資料保存狀態下不需要刷新儲存單元的資料，因此在靜態功耗方面也下降很多。隨著RRAM技術的進一步發展與成熟，基於RRAM所做的TCAM可能在某些應用上具有更大的優勢。

摘要(英)

With the development of Artificial Intelligence (AI), the emphasis on large memory capacity and low-power consumption has become the mainstream of chip design. In order to achieve high memory capacity and low-power consumption, NAND FLASH is the mainstream of non-volatile memory because of its low cost and low-power consumption, but its read and write speed is slower. With the rapid development of the emerging memory technologies recently, the RRAM has faster read and write capability and reliability , compared to NAND Flash memory. Therefore, the RRAM becomes the most promising candidate in terms of its smaller size, low-power consumption and simple manufacturing process.
In this thesis, we have proposed a multi-bit-storage technology using the RRAM 1-transistorand 1-RRAM array. The 1 transistor (T) in 1T1R is a control transistor to control access of the RRAM cell, and the 1 RRAM (R) is a metal-insulator-metal (MIM) structure. The use of continuous linear gradual tuning scheme to operating the SET and RESET operation can effectively extend the the memory window. The designed RRAM can achieve multi-bit storage in both low resistance states (LRS) and high resistance states (HRS). The multi-bit storage method is advantageous to realize the operation of Ternary Content Addressable Memories (TCAM) because the TCAM stores three states, including the logic “1”, the logic “0” and the “don’t care” state. We define the LRS as the logic “1” and the HRS as the logic “0”.As a result, we need to find a stable resistive state between the LRS and HRS to define the “don’t care” state to realize the operation of the TCAM.
In comparison of the traditional the SRAM-based TCAM, the size of the RRAM-based one is much smaller . The RRAM array with a capacity of 1Mb1-Mb with an unit area of 0.0079 um2, and the difference of the memory window between the low-resistance state and high-resistance state can be up to near 200 times. As far as the multi-bit storage performance is concerned, there are 10 states in the low-resistance states and 15 states in the high-resistance states, leading to total 25 states, which can effectively improve the storage density of the 1T1R RRAM array. With the further development and maturity of the mult-bit-storage 1T1R RRAM technology, RRAM-based TCAM may have a greater advantage in future in-memory-searching applications.

關鍵字(中)

★ 電阻式隨機存取記憶體
★ 非揮發性三元內容定址記憶體
★ 非揮發性記憶體

關鍵字(英)

論文目次

目錄
摘要........................................................................................................................................I
Abstract................................................................................................................................III
致謝...................................................................................................................................... V
圖目錄.............................................................................................................................. VIII
表目錄.................................................................................................................................IX
一、導論............................................................................................................................... 1
1.1 背景........................................................................................................................... 1
1.2 研究動機................................................................................................................... 3
1.3 論文架構................................................................................................................... 4
二、RRAM Three-bit per cell 介紹與 TCAM 應用............................................................ 7
2.1 Two-bit per cell 介紹 ............................................................................................... 7
2.2 CAM、TCAM 介紹................................................................................................ 7
2.3 SRAM TCAM 介紹.................................................................................................. 8
2.4 RRAM TCAM 介紹.................................................................................................. 9
2.5 實驗設置................................................................................................................ 10
三、1-Mb 1T-1R RRAM Array .......................................................................................... 16
3.1 介紹......................................................................................................................... 16
3.2 Unit Cell 結構........................................................................................................ 16
3.3 操作條件................................................................................................................ 18
3.4 1-Mb 1T-1R RRAM 矩陣架構.............................................................................. 19
3.5 電壓感測放大器.................................................................................................... 19
3.6 閃存型類比數位轉換器........................................................................................ 20
3.7 正電壓位準偏移器 (Positive Level Shifter) ........................................................ 21
四、實驗結果..................................................................................................................... 37
4.1 Shmoo 圖 (FORMing/SET/RESET/Read Shmoo Plot)......................................... 37
4.2 Unit Cell 電阻分布圖 ........................................................................................... 38
4.3 連續電阻漸進調變電阻分布圖 (Resistance Continually Gradual Tuning)........ 39
VII
4.4 Multi level cell 電阻分布圖 ................................................................................. 39
4.5 耐久度測試 (Endurance)...................................................................................... 40
4.6 資料保存時間 (Retention Time) .......................................................................... 41
4.7 記憶體輸出資料量測 (Output Data).................................................................... 42
五、結論............................................................................................................................. 59
參考文獻............................................................................................................................. 64

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指導教授

謝易叡

審核日期

2023-12-21

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