博碩士論文 110521068 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:54 、訪客IP:18.117.102.227
姓名 李冠逸(Kuan-Yi Lee)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 40奈米之電阻式記憶體陣列透過啟動/設置/重置操作物理不可複製功能的綜合研究
(Comprehensive Studies of the RRAM Operations (FORMing,SET,RESET) Induced Physical Unclonable Functions (PUFs) on 40-nm RRAM Array)
相關論文
★ 基於十六奈米鰭式場效電晶體平台實現通道轟擊電離編程機制之低成本高速嵌入式動態隨機存取記憶體★ 具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現
★ 通過虛擬源極傳輸模型對16-nm應變矽鰭式場效電晶體低溫準彈道傳輸的電性變化建模★ 基於閾值電壓電性擾動所實現之高速亂數產生率的40-nm 4T-SRAM真亂數產生器記憶體矩陣晶片
★ 多阻態存取1T1R電阻式記憶體矩陣晶片的三態內容定址記憶體的設計和實現★ 新穎的多阻態之真亂數產⽣器由 40nm電阻式記憶體陣列實現
★ 新穎極小化高密度三維整體堆疊式1T-nF電流熔絲一次性編程記憶體晶片★ 混和訊號 1.6-3.6GHz 相位旋轉延遲鎖定迴路
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 (2029-1-10以後開放)
摘要(中) 在資訊安全時代之中,資料保護是很重要的一環,現在已經無法單純靠軟體來防護,在硬體安全防護方面,物理不可複製功能(Physical Unclonable Function, PUF)成為新的課題發展,靠著硬體本身製程上的變異性形成隨機字串而防止資料經由駭客盜取,在傳統揮發式記憶體的SRAM、DRAM已經逐漸達到物理極限,但另一方面,非揮發式記憶體較有發展空間,其主要面積大小、能耗和成本問題都能比揮發式記憶體中來的較佳,所以本篇論文探討利用電阻式記憶體為基礎設計一個1T1R陣列來實現以及驗證PUF功能,透過利用三種操作模式對電阻式記憶體的編程,使電阻式記憶體的阻態改變來區分記憶體儲存狀態0或1的訊號,並且利用這0與1訊號來進行PUF運用。
在實驗結果方面,可以看出在三種操作下以及兩種不同溫度下的情況來說,以SET操作方面較有各項的優勢,且在數據統計分析上,三種狀況下皆具有獨特性(Inter Hamming Distance)、可靠度(Intra Hamming Distance)和均勻性(Hamming Weight)等等,其在自相關係數(Auto correlation Function)也是都在95%區間之內,表示字串之間的相關性極低,本實驗三種操作狀態在25度常溫與75度高溫下皆通過美國國家標準與技術研究院(NIST)的15項字串隨機標準,並且進行分析使用XOR機制來進行PUF增強功能,增強安全性且能有效避免機器學習的建模攻擊以及側信道攻擊,因此本論文提出的設計利用大型陣列施行PUF功能,且能有效提高效率、增加安全強度係數與有效避免駭客攻擊。
摘要(英) In the era of information security, data protection plays a crucial role, and it is no longer sufficient to rely on software for defense. Physical Unclonable Function (PUF) has emerged as a new frontier in the realm of hardware security. PUF leverages the inherent variability in the fabrication process of hardware to generate random strings, serving as a deterrent against data theft by hackers. Traditional volatile memory types, such as the SRAM and DRAM have gradually reached their physical limits. However, non-volatile memory (NVM) appears to offer more developmental potential, with advantages in terms of area size, power consumption, and cost, compared to volatile memory. Therefore, this paper explores the design and verification of a 1T1R array based on the RRAM to implement and validate PUF functionality.
Through three operational modes for programming resistive memory, the resistance state changes are utilized to differentiate between the stored signals representing 0 or 1 in the memory. The experiment results demonstrate that the SETSET operation exhibits superior performance in various aspects under three operational modes and two different temperature conditions. Statistical analysis shows that all three scenarios exhibit uniqueness (Inter hamming distance), reliability (Intra hamming distance), uniformity (Hamming weight), and low correlation between strings.
Furthermore, the proposed design passes NIST test at both room temperature (25 Celsius degrees) and high temperature (75 Celsius degrees). This paper introduces the use of the XOR mechanism to enhance the PUF function, thereby improving security and effectively mitigating machine learning modeling attacks and side-channel attacks. In conclusion, the designed PUF implementation utilizing a large-scale array proves to be efficient, enhances security strength, and effectively guards against hacker attacks.
關鍵字(中) ★ 電阻式記憶體
★ 物理不可複製功能
★ 硬體資安
關鍵字(英) ★ Resistive memory
★ Physical Unclonable Function
★ Hardware Security
論文目次 摘要
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 導論 1
1.1 背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 文獻回顧 4
2.1 揮發性記憶體與非揮發性記憶體介紹 4
2.2 磁阻式記憶體MRAM 5
2.3 相變式記憶體Phase Change RAM 6
2.4 一次性可編程記憶體OTP 7
2.5 電阻式記憶體RRAM 9
2.6 電阻式記憶體RRAM 操作方式 10
2.7 電阻式記憶體RRAM PUF優勢 11
第三章 RRAM-PUF 物理不可複製函數實驗 20
3.1 PUF(Physical Unclonable Function)介紹 20
3.2 PUF操作 21
3.3 Unit cell 22
3.4 1T1R 陣列 22
3.5 實驗設置與方法 22
第四章 量測結果 28
4.1 Shmoo Plot 28
4.2 Resistance Plot 29
4.3 MOSAIC Plots 30
4.4 Inter Hamming Distance Plots 31
4.5 Intra Hamming Distance Plots 32
4.6 Hamming Weight Plots 32
4.7 Auto Correlation Function 33
4.8 XOR Improvement 33
4.9 Drift Current 34
4.10 NIST Tests 34
第五章 結論 61
參考文獻 67
參考文獻 [1] E. I. Vatajelu, G. Di Natale, M. Indaco and P. Prinetto, "STT MRAM-based PUFs," 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2015, pp. 872-875, doi: 10.7873/DATE.2015.0505.,
[2] Feng Li, Xiaoyu Yang, A. T. Meeks, J. T. Shearer and K. Y. Le, "Evaluation of SiO/sub 2/ antifuse in a 3D-OTP memory," in IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3, pp. 416-421, Sept. 2004, doi: 10.1109/TDMR.2004.837118.
[3] V. Parmar , Sandeep Kaur Kingra, Deepak Verma, Digamber Pandey, Giuseppe Piccolboni, Alessandro Bricalli, Amir Regev, Gabriel Pares, Laurent Grenouillet, Jean-Francois Nodin and Manan Suri, "Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device array," 2023 IEEE International Memory Workshop (IMW), Monterey, CA, USA, 2023, pp. 1-4, doi: 10.1109/IMW56887.2023.10145993.
[4] S. K. Mathew, S. K. Satpathy, M. A. Anders, Himanshu Kaul, S. K. Hsu, A. Agarwal, G. K. Chen, R. J. Parker, R. K. Krishnamurthy, Vivek De, "16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 278-279, doi: 10.1109/ISSCC.2014.6757433.
[5] Jiahao Song, Haoyang Luo, Xiyuan Tang, Kuan Xu, Zhigang Ji, Yuan Wang, Runsheng Wang, Ru Huang, "A 3T eDRAM In-Memory Physically Unclonable Function With Spatial Majority Voting Stabilization," in IEEE Solid-State Circuits Letters, vol. 5, pp. 58-61, 2022, doi: 10.1109/LSSC.2022.3158630.
[6] Rashid. Ali, You Wang, Haoyuan Ma, Zhengyi Hou, Deming Zhang, Erya Deng, and Weisheng Zhao, "A Reconfigurable Arbiter PUF Based on STT-MRAM," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401053.
[7] J. Das, K. Scott, S. Rajaram, D. Burgett and S. Bhanja, "MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS," in IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 436-443, May 2015, doi: 10.1109/TNANO.2015.2397951.
[8] L. Cattaneo., M. Baldo, N. Lepri, F. Sancandi, M. Borghi, E. Petroni, A. Serafini, R. Annunziata, A. Redaelli and D. Ielmini, "Enhancing reliability of a strong physical unclonable function (PUF) solution based on virgin-state phase change memory (PCM)," 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, pp. 1-6, doi: 10.1109/IRPS48203.2023.10117586.
[9] L. Zhang, Z. H. Kong, C. -H. Chang, A. Cabrini and G. Torelli, "Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions," in IEEE Transactions on Information Forensics and Security, vol. 9, no. 6, pp. 921-932, June 2014, doi: 10.1109/TIFS.2014.2315743.
[10] E. R. Hsieh, H. W. Wang, C. H. Liu, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen and Osbert Cheng, "Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era," 2019 Symposium on VLSI Technology, Kyoto, Japan, 2019, pp. T118-T119, doi: 10.23919/VLSIT.2019.8776515.
[11] W. C. Wang, C. C. Chuang, C. W. Chang, E. R. Hsieh, H. W. Chen and S. S. Chung, "A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 31.6.1-31.6.4, doi: 10.1109/IEDM13553.2020.9371898.
[12] S. Sadana, A. Lele, S. Tsundus, P. Kumbhare and U. Ganguly, "A Highly Reliable and Unbiased PUF Based on Differential OTP Memory," in IEEE Electron Device Letters, vol. 39, no. 8, pp. 1159-1162, Aug. 2018, doi: 10.1109/LED.2018.2844557.
[13] A. Lele, S. Sadana, A. Singh, H. S. Jatana and U. Ganguly, "A simple PECVD SiO2 OTP memory based PUF for 180nm node for IoT," 2017 75th Annual Device Research Conference (DRC), South Bend, IN, USA, 2017, pp. 1-2, doi: 10.1109/DRC.2017.7999433.
[14] B. Lin, B. Gao, Y. Pang, J. Tang, H. Qian and H. Wu, "A Unified Memory and Hardware Security Module Based on the Adjustable Switching Window of Resistive Memory," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 1257-1265, 2020, doi: 10.1109/JEDS.2020.3019266.
[15] B. Hajri, M. M. Mansour, A. Chehab and H. Aziza, "A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications," 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Frascati, Italy, 2020, pp. 1-4, doi: 10.1109/DFT50435.2020.9250829.
[16] A. Chen, "Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions," in IEEE Electron Device Letters, vol. 36, no. 2, pp. 138-140, Feb. 2015, doi: 10.1109/LED.2014.2385870.
[17] H. Zhuang, X. Xi, N. Sun and M. Orshansky, "A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 1, pp. 135-144, Jan. 2020, doi: 10.1109/TCSI.2019.2945247.
[18] J. Liu, Y. Zhao, Y. Zhu, C. -H. Chan and R. P. Martins, "A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4898-4907, Dec. 2022, doi: 10.1109/TCSI.2022.3206214.
[19] Y. He, D. Li, Z. Yu and K. Yang, "36.5 An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3×10-8 Bit Error Rate," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 506-508, doi: 10.1109/ISSCC42613.2021.9365741.
[20] L. Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. Franca, Sandip Kundu, "Realizing strong PUF from weak PUF via neural computing," 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Cambridge, UK, 2017, pp. 1-6, doi: 10.1109/DFT.2017.8244433.
[21] P. Williams, H. Idriss and M. Bayoumi, "Mc-PUF: Memory-based and Machine Learning Resilient Strong PUF for Device Authentication in Internet of Things," 2021 IEEE International Conference on Cyber Security and Resilience (CSR), Rhodes, Greece, 2021, pp. 61-65, doi: 10.1109/CSR51186.2021.9527930.
[22] H. Li, Y. Jin, K. Han and D. Yu, "A Lightweight XOR-PUF Structure for Resource Constrained Smart Device," 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), Osaka, Japan, 2019, pp. 168-169, doi: 10.1109/GCCE46687.2019.9015230.
[23] Y. Pang, B. Gao, D. Wu, S. Yi, Q. Liu, W.H. Chen, T.W. Chang, W.E. Lin, X. Sun, S. Yu, H. Qian, M.F. Chang, H.Wu, et al., "25.2 A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10−6 Native Bit Error Rate," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 402-404, doi: 10.1109/ISSCC.2019.8662307.
[24] B. Lin, Y. Pang, B.Gao, J. Tang, D. Wu, T. W. Chang, W. E. Lin, X.Sun, S. Yu, M. F. Chang, H. Qian, H.Wu, "A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source," in IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1641-1650, May 2021, doi: 10.1109/JSSC.2021.3050295.
[25] K.-H. Chuang, E. Bury, R. Degraeve, B. Kaczer, T. Kallstenius, G. Groeseneken, D. Linten, I. Verbauwhede, "A multi-bit/cell PUF using analog breakdown positions in CMOS," 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, USA, 2018, pp. P-CR.2-1-P-CR.2-5, doi: 10.1109/IRPS.2018.8353655.
[26] Y. Shifman, A. Miller, O. Keren, Y. Weizmann and J. Shor, "A Method to Improve Reliability in a 65-nm SRAM PUF Array," in IEEE Solid-State Circuits Letters, vol. 1, no. 6, pp. 138-141, June 2018, doi: 10.1109/LSSC.2018.2879216.
[27] B. Gao, B. Lin, X. Li, J. Tang, H. Qian and H. Wu, "A Unified PUF and TRNG Design Based on 40-nm RRAM With High Entropy and Robustness for IoT Security," in IEEE Transactions on Electron Devices, vol. 69, no. 2, pp. 536-542, Feb. 2022, doi: 10.1109/TED.2021.3138365.
[28] X. Xue, J. Yang, Y. Zhang, M. Wang, H. Lv, X. Zeng, M. Liu, "A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key," 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, Macao, 2019, pp. 29-32, doi: 10.1109/A-SSCC47793.2019.9056893.
[29] M. -Y. Wu, T. H. Yang, L. C. Chen, C. C. Lin, H. C. Hu, F. Y. Su, C. M. Wang, J. P. H. Huang, H. M. Chen, C. C-H. Lu, E. C-S. Yang, R. S-J. Shen. "A PUF scheme using competing oxide rupture with bit error rate approaching zero," 2018 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 130-132, doi: 10.1109/ISSCC.2018.8310218.
[30] R. Giterman, Y. Weizman and A. Teman, "Gain-Cell Embedded DRAM-Based Physical Unclonable Function," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4208-4218, Dec. 2018, doi: 10.1109/TCSI.2018.2838331.
[31] D. Y. Wang, Y. C. Hsin, K. Y. Lee, G. L. Chen, S. Y. Yang, H. H. Lee, Y. J. Chang, I. J. Wang, Y. C. Kuo, Y. S. Chen, P. H. Wang, C. I. Wu, D. D. Tang, "Hardware implementation of physically unclonable function (puf) in perpendicular STT MRAM," 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, 2017, pp. 1-2, doi: 10.1109/VLSI-TSA.2017.7942497.
指導教授 謝易叡(E-Ray Hsieh) 審核日期 2024-1-11
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明