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姓名	林祐丞(You-Cheng Lin)  查詢紙本館藏	畢業系所	資訊工程學系
論文名稱	TrustFADE: 針對可程式化邏輯區塊之安全認證方法 (TrustFADE: An Anti-theft Attestation Design for Programmable Logic)
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中)	現今很多嵌入式系統開發商將現場可程式化邏輯閘陣列 (FPGA) 的設計外包給知識產權 (IP) 設計公司。為了保護他們的 IP 設計 (FPGA的配置) 免受篡改，需要一種安全的認證方法。在本文中，我們提出了一種針對 Xilinx Ultrascale+ MPSoC 架構的 FPGA 的安全認證方法。而在認證之前需要一個讀回 FPGA 的配置。然而，Xilinx Ultrascale+ MPSoC 讀回方法很容易受到攻擊。而傳統的 FPGA 認證方法在 FPGA 內部實現認證模組，消耗了大量的 FPGA 資源。在我們的方法中，我們禁用了 Xilinx Ultrascale+ MPSoC 中的讀回流程。攻擊者無法訪問 FPGA 的配置。我們利用可信執行環境 (TEE) 安全地讀回 FPGA 的配置，而不需要消耗 FPGA 的資源。我們的證明模組可以安全地認證 FPGA 的執行狀態。分析和實驗表明，我們的設計可以安全地讀回 FPGA 的配置並對其進行認證。
摘要(英)	Nowadays, many embedded system developers outsource the designs of Field Programmable Gate Array (FPGA) to Intellectual Property (IP) design houses. To protect their IP designs (the configuration of FPGA) from tamper attack, a secure attestation method is necessary. In this paper, we propose a secure attestation method for FPGA in Xilinx Ultrascale+ MPSoC architecture. To attest the configuration of FPGA, a readback process is needed before attestation. However, Xilinx Ultrascale+ MPSoC readback method is vulnerable. Traditional attestation methods for FPGA implement their attestation module in FPGA, which consumes lots of resources of FPGA. In our method, we disable the readback flow in Xilinx Ultrascale+ MPSoC. The adversaries cannot access the configuration of FPGA. We leverage Trusted Execution Environment (TEE) to readback the configuration status of FPGA securely, which does not need to consume the resources of FPGA. Our attestation module can securely attest to the execution status of FPGA. Analysis and experimental results show that our design can readback the configuration of FPGA securely and attest it efficiently.
關鍵字(中)	★ FPGA 讀回 ★ 故障回復 ★ IP 竊盜 ★ 可信執行環境 ★ ARM TrustZone	關鍵字(英)	★ FPGA Readback ★ Failure Recovery ★ IP theft ★ Trusted Execution Environment ★ ARM TrustZone
論文目次	中文摘要 i Abstract ii 致謝 iii Contents iv List of Figures vi List of Tables viii 1 Introduction 1 2 Background 3 2.0.1 Trusted Execution Environment 3 2.0.2 ARM Trustzone 3 2.0.3 Zynq UltraScale+ MPSoC Architecture 6 2.0.4 TCG Guidance for Secure Update on Embedded System 7 2.0.5 Remote attestation 8 2.0.6 FPGAs 8 2.0.7 Configuration Interfaces 9 3 Related Works 11 3.0.1 The implementation of Xilinx Ultrascale+ MPSoC readback method 11 3.0.2 Attestation model in FPGA 12 4 System Model 14 4.0.1 System Assumptions 14 4.0.2 Threat Model 14 4.0.3 Attack out of scope 14 5 Secure PL Configuration Readback Design 16 5.0.1 Disable interface to avoid PL configuration unauthorized access 17 5.0.2 TrustFADE Readback and Attestation Method 18 5.0.3 Components of System Architecture 22 6 Secure PL Configuration Readback Implementation 26 6.0.1 Custom PMU firmware 26 6.0.2 Memory allocation issue 27 6.0.3 Readback Command Format 28 6.0.4 Secure storage and Hash function 30 6.0.5 PL Manager Pseudo TA 30 6.0.6 Secure Driver 31 6.0.7 Details of Readback flow 31 7 Evaluation 34 7.0.1 Security Analysis 34 7.0.2 Performance Evaluation 37 8 Conclusion 39 Bibliography 40
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指導教授	張貴雲 何錦文(Guey-Yun Chang Chin-Wen Ho)	審核日期	2023-8-9
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