| 姓名 |
吳政勳(Cheng-Shing Wu)
查詢紙本館藏 |
畢業系所 |
電機工程學系 |
| 論文名稱 |
一個高速╱低複雜度旋轉方法的統一設計架構：角度量化的觀點
(A UNIFIED DESIGN FRAMEWORK OF HIGH-SPEED/LOW-COST ROTATION ENGINES:AN ANGLE QUANTIZATION PERSPECTIVE)
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| 相關論文 | |
| 檔案 |
 [Endnote RIS 格式]
[Bibtex 格式]
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| 摘要(中) |
向量旋轉（Vector Rotation）在許多數位信號處理（DSP）的應用中被廣泛地使用。在
這篇論文中，我們首先引入一個新的設計概念，稱之為角度量化（Angle
Quantization）。當所需的旋轉角度是事先預知的情形下，角度量化的概念可用來當
作一個設計的指標。以此角度量化為基礎，我們建立了一個統一的低複雜度╱高速度旋
轉演算法的設計架構（Design Framework）。數個現有的向量旋轉演算法，例如傳統座
標旋轉數位計算器（CORDIC）演算法、角度重新編碼（Angle Recoding）演算法、修改
之座標旋轉數位計算器（MVR-CORDIC）演算法、以及延伸基礎角度集合（EEAS）演算法
等均可套入這個統一的設計架構；這些演算法亦組成了所謂的向量旋轉座標旋轉數位計
算器家族（Vector Rotational CORDIC Family）。此外，對於上述的演算法我們也提
出了其相對應的最佳化搜尋演算法（Optimization Searching Algorithm）、比例修正
（Scaling Operation）、訊號量化雜訊比增進法（SQNR Refinement）、系統化的設計
流程（Systematic Design Flow）以及超大型積體電路架構。所有的演算法均有設計範
例來加以說明，且輔以完整的電腦模擬來證明其正確性。以此新的設計架構為基礎，我
們不僅可以實現高速度╱低複雜度的向量旋轉超大型積體電路架構，同時無須犧牲在定
點實現（Fixed-point Implementation）時的準確度。 |
| 摘要(英) |
Vector rotation is the key operation employed extensively in many digital
signal processing (DSP) applications. In this dissertation, we introduce a new
design concept called Angle Quantization (AQ). It can be used as a design
index for vector rotational operation, where the rotational angle is known in
advance. Based on the AQ process, we establish a unified design framework for
cost-effective low-latency rotational algorithms and architectures. Several
existing works, such as conventional CORDIC, AR-CORDIC, MVR-CORDIC, and
EEAS-based CORDIC algorithm, can be fitted into the design framework, forming a
Vector Rotational CORDIC Family. In addition, for MVR-CORDIC and
EEAS-based CORDIC algorithm, we address their corresponding optimization
searching algorithms, scaling operations, SQNR refinement schemes, systematic
design flow, and VLSI architectures. All the statements are supported by
extensive computer simulations and design examples. Based on the new design
framework, we can realize high-speed/low-complexity rotational VLSI circuits,
whereas without degrading the precision performance in fixed-point
implementations. |
| 關鍵字(中) |
★ 座標旋轉數位計算器
★ 超大型積體電路
★ 向量旋轉 |
關鍵字(英) |
★ Vector Rotation
★ VLSI
★ CORDIC |
| 論文目次 |
Abstract i
Acknowledgement iii
{1}Introduction}{1}
{1.1}Digital Filters}{2}
{1.2}Orthogonal Transformations}{6}
{1.3}Research Focus and Contributions}{9}
{1.3.1}Vector Rotation}{9}
{1.3.2}Definition of Vector Rotation}{10}
{1.3.3}Main Contributions}{11}
{1.4}Thesis Organization}{14}
{2}Angle Quantization Process and CORDIC Algorithm}{16}
{2.1}Concept of Angle Quantization}{16}
{2.1.1}Angle Quantization Process and SPT}{18}
{2.2}Conventional CORDIC Algorithm}{19}
{3}Modified Vector Rotational CORDIC Algorithm}{25}
{3.1}The MVR-CORDIC Algorithm}{26}
{3.2}Searching Algorithms and Comparisons}{29}
{3.2.1}Searching Algorithms}{29}
{3.2.2}Comparison of Computational Complexity and Error Performance}{32}
{3.3}Relationship between Error Performance and Design Parameters}{35}
{3.3.1}Error performance vs. number of elementary angles N}{36}
{3.3.2}Error performance vs. restricted iteration number Rm}{37}
{3.3.3}Error performance vs. searching block length D}{38}
{3.4}Selective Pre-rotation Scheme}{38}
{3.4.1}Conventional Pre-rotation Scheme}{38}
{3.4.2}Selective Pre-rotation Scheme}{40}
{3.4.3}Design Example and Simulation}{40}
{3.5}Selective Scaling Scheme}{43}
{3.5.1}Conventional Scaling Operations}{43}
{3.5.2}Selective Scaling Scheme}{45}
{3.5.3}Design Example}{46}
{3.6}Iteration-tradeoff Scheme and Design Flow}{47}
{3.6.1}Iteration-tradeoff Scheme for Rm and Rs}{47}
{3.6.2}Design Flow for the MVR-CORDIC Algorithm}{49}
{3.6.3}Design Example}{51}
{3.7}VLSI Implementation of MVR-CORDIC}{54}
{3.7.1}Iterative MVR-CORDIC Structure}{54}
{3.7.2}Parallel and Pipelined MVR-CORDIC Structure}{56}
{4}Extended Elementary Angle Set-Based CORDIC Algorithm}{58}
{4.1}Extended Elementary-Angle Set (EEAS)}{59}
{4.2}Searching Algorithms of the EEAS Scheme}{63}
{4.2.1}Greedy Algorithm}{64}
{4.2.2}Trellis-based Searching (TBS) Algorithm}{64}
{4.2.3}Error Bound of TBS Algorithm}{69}
{4.2.4}Comparison of Computational Complexity}{71}
{4.3}Performance Comparisons}{74}
{4.3.1}EEAS Scheme vs. AR Technique {74}
{4.3.2}Trellis-based Searching (TBS) Algorithm vs. Greedy Algorithm}{75}
{4.3.3}Combination of EEAS Scheme and the TBS Algorithm}{77}
{4.4}Scaling Phase of the EEAS Scheme}{78}
{4.4.1}The Extended Type-II (ET-II) Scaling Operation}{78}
{4.4.2}Simulations}{79}
{4.5}Combination of Micro-rotation Phase and Scaling Phase}{80}
{4.5.1}Design Example}{80}
{4.5.2}Simulation of complete EEAS-based CORDIC Algorithm}{81}
{4.6}VLSI Structures of the EEAS-based CORDIC Algorithm}{83}
{5}Vector Rotational CORDIC Family}{87}
{5.1}Link AQ Process with Conventional CORDIC algorithm}{87}
{5.2}Link AQ Process with the AR Technique}{89}
{5.3}Link AQ Process with MVR-CORDIC Algorithm}{91}
{5.4}Link AQ Process with EEAS-based CORDIC Algorithm}{92}
{5.5}Generalized EEAS Scheme}{93}
{5.6}Family of Vector Rotational CORDIC Algorithm}{94}
{6}Conclusions and Future Researches}{96}
{A}Analysis of SQNR}{100} |
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| 指導教授 |
周世傑、吳安宇
(Shyh-Jye Jou、An-Yeu Wu)
|
審核日期 |
2002-7-11 |
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